1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2017 Intel Deutschland GmbH
9 * Copyright(c) 2018 - 2019 Intel Corporation
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
22 * Copyright(c) 2017 Intel Deutschland GmbH
23 * Copyright(c) 2018 - 2019 Intel Corporation
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 *
30 * * Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * * Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in
34 * the documentation and/or other materials provided with the
35 * distribution.
36 * * Neither the name Intel Corporation nor the names of its
37 * contributors may be used to endorse or promote products derived
38 * from this software without specific prior written permission.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 *
52 *****************************************************************************/
53 #include "iwl-trans.h"
54 #include "iwl-prph.h"
55 #include "iwl-context-info.h"
56 #include "iwl-context-info-gen3.h"
57 #include "internal.h"
58 #include "fw/dbg.h"
59
60 /*
61 * Start up NIC's basic functionality after it has been reset
62 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
63 * NOTE: This does not load uCode nor start the embedded processor
64 */
65 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
66 {
67 int ret = 0;
68
69 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
70
71 /*
72 * Use "set_bit" below rather than "write", to preserve any hardware
73 * bits already set by default after reset.
74 */
75
76 /*
77 * Disable L0s without affecting L1;
78 * don't wait for ICH L0s (ICH bug W/A)
79 */
80 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
81 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
82
83 /* Set FH wait threshold to maximum (HW error during stress W/A) */
84 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
85
86 /*
87 * Enable HAP INTA (interrupt from management bus) to
88 * wake device's PCI Express link L1a -> L0s
89 */
90 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
91 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
92
93 iwl_pcie_apm_config(trans);
94
95 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
96 if (ret)
97 return ret;
98
99 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
100
101 return 0;
102 }
103
104 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
105 {
106 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
107
108 if (op_mode_leave) {
109 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
110 iwl_pcie_gen2_apm_init(trans);
111
112 /* inform ME that we are leaving */
113 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
114 CSR_RESET_LINK_PWR_MGMT_DISABLED);
115 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
116 CSR_HW_IF_CONFIG_REG_PREPARE |
117 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
118 mdelay(1);
119 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
120 CSR_RESET_LINK_PWR_MGMT_DISABLED);
121 mdelay(5);
122 }
123
124 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
125
126 /* Stop device's DMA activity */
127 iwl_pcie_apm_stop_master(trans);
128
129 iwl_trans_sw_reset(trans);
130
131 /*
132 * Clear "initialization complete" bit to move adapter from
133 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
134 */
135 iwl_clear_bit(trans, CSR_GP_CNTRL,
136 BIT(trans->trans_cfg->csr->flag_init_done));
137 }
138
139 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
140 {
141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
142
143 lockdep_assert_held(&trans_pcie->mutex);
144
145 if (trans_pcie->is_down)
146 return;
147
148 trans_pcie->is_down = true;
149
150 /* tell the device to stop sending interrupts */
151 iwl_disable_interrupts(trans);
152
153 /* device going down, Stop using ICT table */
154 iwl_pcie_disable_ict(trans);
155
156 /*
157 * If a HW restart happens during firmware loading,
158 * then the firmware loading might call this function
159 * and later it might be called again due to the
160 * restart. So don't process again if the device is
161 * already dead.
162 */
163 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
164 IWL_DEBUG_INFO(trans,
165 "DEVICE_ENABLED bit was set and is now cleared\n");
166 iwl_pcie_gen2_tx_stop(trans);
167 iwl_pcie_rx_stop(trans);
168 }
169
170 iwl_pcie_ctxt_info_free_paging(trans);
171 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560)
172 iwl_pcie_ctxt_info_gen3_free(trans);
173 else
174 iwl_pcie_ctxt_info_free(trans);
175
176 /* Make sure (redundant) we've released our request to stay awake */
177 iwl_clear_bit(trans, CSR_GP_CNTRL,
178 BIT(trans->trans_cfg->csr->flag_mac_access_req));
179
180 /* Stop the device, and put it in low power state */
181 iwl_pcie_gen2_apm_stop(trans, false);
182
183 iwl_trans_sw_reset(trans);
184
185 /*
186 * Upon stop, the IVAR table gets erased, so msi-x won't
187 * work. This causes a bug in RF-KILL flows, since the interrupt
188 * that enables radio won't fire on the correct irq, and the
189 * driver won't be able to handle the interrupt.
190 * Configure the IVAR table again after reset.
191 */
192 iwl_pcie_conf_msix_hw(trans_pcie);
193
194 /*
195 * Upon stop, the APM issues an interrupt if HW RF kill is set.
196 * This is a bug in certain verions of the hardware.
197 * Certain devices also keep sending HW RF kill interrupt all
198 * the time, unless the interrupt is ACKed even if the interrupt
199 * should be masked. Re-ACK all the interrupts here.
200 */
201 iwl_disable_interrupts(trans);
202
203 /* clear all status bits */
204 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
205 clear_bit(STATUS_INT_ENABLED, &trans->status);
206 clear_bit(STATUS_TPOWER_PMI, &trans->status);
207
208 /*
209 * Even if we stop the HW, we still want the RF kill
210 * interrupt
211 */
212 iwl_enable_rfkill_int(trans);
213
214 /* re-take ownership to prevent other users from stealing the device */
215 iwl_pcie_prepare_card_hw(trans);
216 }
217
218 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
219 {
220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
221 bool was_in_rfkill;
222
223 mutex_lock(&trans_pcie->mutex);
224 trans_pcie->opmode_down = true;
225 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
226 _iwl_trans_pcie_gen2_stop_device(trans);
227 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
228 mutex_unlock(&trans_pcie->mutex);
229 }
230
231 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
232 {
233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
234 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
235 trans->cfg->min_txq_size);
236
237 /* TODO: most of the logic can be removed in A0 - but not in Z0 */
238 spin_lock(&trans_pcie->irq_lock);
239 iwl_pcie_gen2_apm_init(trans);
240 spin_unlock(&trans_pcie->irq_lock);
241
242 iwl_op_mode_nic_config(trans->op_mode);
243
244 /* Allocate the RX queue, or reset if it is already allocated */
245 if (iwl_pcie_gen2_rx_init(trans))
246 return -ENOMEM;
247
248 /* Allocate or reset and init all Tx and Command queues */
249 if (iwl_pcie_gen2_tx_init(trans, trans_pcie->cmd_queue, queue_size))
250 return -ENOMEM;
251
252 /* enable shadow regs in HW */
253 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
254 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
255
256 return 0;
257 }
258
259 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
260 {
261 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
262
263 iwl_pcie_reset_ict(trans);
264
265 /* make sure all queue are not stopped/used */
266 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
267 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
268
269 /* now that we got alive we can free the fw image & the context info.
270 * paging memory cannot be freed included since FW will still use it
271 */
272 iwl_pcie_ctxt_info_free(trans);
273
274 /*
275 * Re-enable all the interrupts, including the RF-Kill one, now that
276 * the firmware is alive.
277 */
278 iwl_enable_interrupts(trans);
279 mutex_lock(&trans_pcie->mutex);
280 iwl_pcie_check_hw_rf_kill(trans);
281 mutex_unlock(&trans_pcie->mutex);
282 }
283
284 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
285 const struct fw_img *fw, bool run_in_rfkill)
286 {
287 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
288 bool hw_rfkill;
289 int ret;
290
291 /* This may fail if AMT took ownership of the device */
292 if (iwl_pcie_prepare_card_hw(trans)) {
293 IWL_WARN(trans, "Exit HW not ready\n");
294 ret = -EIO;
295 goto out;
296 }
297
298 iwl_enable_rfkill_int(trans);
299
300 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
301
302 /*
303 * We enabled the RF-Kill interrupt and the handler may very
304 * well be running. Disable the interrupts to make sure no other
305 * interrupt can be fired.
306 */
307 iwl_disable_interrupts(trans);
308
309 /* Make sure it finished running */
310 iwl_pcie_synchronize_irqs(trans);
311
312 mutex_lock(&trans_pcie->mutex);
313
314 /* If platform's RF_KILL switch is NOT set to KILL */
315 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
316 if (hw_rfkill && !run_in_rfkill) {
317 ret = -ERFKILL;
318 goto out;
319 }
320
321 /* Someone called stop_device, don't try to start_fw */
322 if (trans_pcie->is_down) {
323 IWL_WARN(trans,
324 "Can't start_fw since the HW hasn't been started\n");
325 ret = -EIO;
326 goto out;
327 }
328
329 /* make sure rfkill handshake bits are cleared */
330 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
331 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
332 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
333
334 /* clear (again), then enable host interrupts */
335 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
336
337 ret = iwl_pcie_gen2_nic_init(trans);
338 if (ret) {
339 IWL_ERR(trans, "Unable to init nic\n");
340 goto out;
341 }
342
343 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560)
344 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
345 else
346 ret = iwl_pcie_ctxt_info_init(trans, fw);
347 if (ret)
348 goto out;
349
350 /* re-check RF-Kill state since we may have missed the interrupt */
351 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
352 if (hw_rfkill && !run_in_rfkill)
353 ret = -ERFKILL;
354
355 out:
356 mutex_unlock(&trans_pcie->mutex);
357 return ret;
358 }