This source file includes following definitions.
- ath10k_ahb_priv
- ath10k_ahb_write32
- ath10k_ahb_read32
- ath10k_ahb_gcc_read32
- ath10k_ahb_tcsr_write32
- ath10k_ahb_tcsr_read32
- ath10k_ahb_soc_read32
- ath10k_ahb_get_num_banks
- ath10k_ahb_clock_init
- ath10k_ahb_clock_deinit
- ath10k_ahb_clock_enable
- ath10k_ahb_clock_disable
- ath10k_ahb_rst_ctrl_init
- ath10k_ahb_rst_ctrl_deinit
- ath10k_ahb_release_reset
- ath10k_ahb_halt_axi_bus
- ath10k_ahb_halt_chip
- ath10k_ahb_interrupt_handler
- ath10k_ahb_request_irq_legacy
- ath10k_ahb_release_irq_legacy
- ath10k_ahb_irq_disable
- ath10k_ahb_resource_init
- ath10k_ahb_resource_deinit
- ath10k_ahb_prepare_device
- ath10k_ahb_chip_reset
- ath10k_ahb_wake_target_cpu
- ath10k_ahb_hif_start
- ath10k_ahb_hif_stop
- ath10k_ahb_hif_power_up
- ath10k_ahb_qca4019_targ_cpu_to_ce_addr
- ath10k_ahb_probe
- ath10k_ahb_remove
- ath10k_ahb_init
- ath10k_ahb_exit
1
2
3
4
5
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/of_device.h>
9 #include <linux/clk.h>
10 #include <linux/reset.h>
11 #include "core.h"
12 #include "debug.h"
13 #include "pci.h"
14 #include "ahb.h"
15
16 static const struct of_device_id ath10k_ahb_of_match[] = {
17 { .compatible = "qcom,ipq4019-wifi",
18 .data = (void *)ATH10K_HW_QCA4019
19 },
20 { }
21 };
22
23 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match);
24
25 #define QCA4019_SRAM_ADDR 0x000C0000
26 #define QCA4019_SRAM_LEN 0x00040000
27
28 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
29 {
30 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0];
31 }
32
33 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
34 {
35 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
36
37 iowrite32(value, ar_ahb->mem + offset);
38 }
39
40 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)
41 {
42 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
43
44 return ioread32(ar_ahb->mem + offset);
45 }
46
47 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)
48 {
49 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
50
51 return ioread32(ar_ahb->gcc_mem + offset);
52 }
53
54 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)
55 {
56 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
57
58 iowrite32(value, ar_ahb->tcsr_mem + offset);
59 }
60
61 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)
62 {
63 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
64
65 return ioread32(ar_ahb->tcsr_mem + offset);
66 }
67
68 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)
69 {
70 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
71 }
72
73 static int ath10k_ahb_get_num_banks(struct ath10k *ar)
74 {
75 if (ar->hw_rev == ATH10K_HW_QCA4019)
76 return 1;
77
78 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
79 return 1;
80 }
81
82 static int ath10k_ahb_clock_init(struct ath10k *ar)
83 {
84 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
85 struct device *dev;
86
87 dev = &ar_ahb->pdev->dev;
88
89 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd");
90 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) {
91 ath10k_err(ar, "failed to get cmd clk: %ld\n",
92 PTR_ERR(ar_ahb->cmd_clk));
93 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV;
94 }
95
96 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref");
97 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) {
98 ath10k_err(ar, "failed to get ref clk: %ld\n",
99 PTR_ERR(ar_ahb->ref_clk));
100 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV;
101 }
102
103 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc");
104 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
105 ath10k_err(ar, "failed to get rtc clk: %ld\n",
106 PTR_ERR(ar_ahb->rtc_clk));
107 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV;
108 }
109
110 return 0;
111 }
112
113 static void ath10k_ahb_clock_deinit(struct ath10k *ar)
114 {
115 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
116
117 ar_ahb->cmd_clk = NULL;
118 ar_ahb->ref_clk = NULL;
119 ar_ahb->rtc_clk = NULL;
120 }
121
122 static int ath10k_ahb_clock_enable(struct ath10k *ar)
123 {
124 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
125 int ret;
126
127 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) ||
128 IS_ERR_OR_NULL(ar_ahb->ref_clk) ||
129 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
130 ath10k_err(ar, "clock(s) is/are not initialized\n");
131 ret = -EIO;
132 goto out;
133 }
134
135 ret = clk_prepare_enable(ar_ahb->cmd_clk);
136 if (ret) {
137 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);
138 goto out;
139 }
140
141 ret = clk_prepare_enable(ar_ahb->ref_clk);
142 if (ret) {
143 ath10k_err(ar, "failed to enable ref clk: %d\n", ret);
144 goto err_cmd_clk_disable;
145 }
146
147 ret = clk_prepare_enable(ar_ahb->rtc_clk);
148 if (ret) {
149 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);
150 goto err_ref_clk_disable;
151 }
152
153 return 0;
154
155 err_ref_clk_disable:
156 clk_disable_unprepare(ar_ahb->ref_clk);
157
158 err_cmd_clk_disable:
159 clk_disable_unprepare(ar_ahb->cmd_clk);
160
161 out:
162 return ret;
163 }
164
165 static void ath10k_ahb_clock_disable(struct ath10k *ar)
166 {
167 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
168
169 clk_disable_unprepare(ar_ahb->cmd_clk);
170
171 clk_disable_unprepare(ar_ahb->ref_clk);
172
173 clk_disable_unprepare(ar_ahb->rtc_clk);
174 }
175
176 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)
177 {
178 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
179 struct device *dev;
180
181 dev = &ar_ahb->pdev->dev;
182
183 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev,
184 "wifi_core_cold");
185 if (IS_ERR(ar_ahb->core_cold_rst)) {
186 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",
187 PTR_ERR(ar_ahb->core_cold_rst));
188 return PTR_ERR(ar_ahb->core_cold_rst);
189 }
190
191 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev,
192 "wifi_radio_cold");
193 if (IS_ERR(ar_ahb->radio_cold_rst)) {
194 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",
195 PTR_ERR(ar_ahb->radio_cold_rst));
196 return PTR_ERR(ar_ahb->radio_cold_rst);
197 }
198
199 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev,
200 "wifi_radio_warm");
201 if (IS_ERR(ar_ahb->radio_warm_rst)) {
202 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",
203 PTR_ERR(ar_ahb->radio_warm_rst));
204 return PTR_ERR(ar_ahb->radio_warm_rst);
205 }
206
207 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev,
208 "wifi_radio_srif");
209 if (IS_ERR(ar_ahb->radio_srif_rst)) {
210 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",
211 PTR_ERR(ar_ahb->radio_srif_rst));
212 return PTR_ERR(ar_ahb->radio_srif_rst);
213 }
214
215 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev,
216 "wifi_cpu_init");
217 if (IS_ERR(ar_ahb->cpu_init_rst)) {
218 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",
219 PTR_ERR(ar_ahb->cpu_init_rst));
220 return PTR_ERR(ar_ahb->cpu_init_rst);
221 }
222
223 return 0;
224 }
225
226 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)
227 {
228 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
229
230 ar_ahb->core_cold_rst = NULL;
231 ar_ahb->radio_cold_rst = NULL;
232 ar_ahb->radio_warm_rst = NULL;
233 ar_ahb->radio_srif_rst = NULL;
234 ar_ahb->cpu_init_rst = NULL;
235 }
236
237 static int ath10k_ahb_release_reset(struct ath10k *ar)
238 {
239 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
240 int ret;
241
242 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
243 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
244 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
245 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
246 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
247 return -EINVAL;
248 }
249
250 ret = reset_control_deassert(ar_ahb->radio_cold_rst);
251 if (ret) {
252 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
253 return ret;
254 }
255
256 ret = reset_control_deassert(ar_ahb->radio_warm_rst);
257 if (ret) {
258 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
259 return ret;
260 }
261
262 ret = reset_control_deassert(ar_ahb->radio_srif_rst);
263 if (ret) {
264 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
265 return ret;
266 }
267
268 ret = reset_control_deassert(ar_ahb->cpu_init_rst);
269 if (ret) {
270 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
271 return ret;
272 }
273
274 return 0;
275 }
276
277 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg,
278 u32 haltack_reg)
279 {
280 unsigned long timeout;
281 u32 val;
282
283
284 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
285 val |= AHB_AXI_BUS_HALT_REQ;
286 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
287
288
289 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT);
290 do {
291 val = ath10k_ahb_tcsr_read32(ar, haltack_reg);
292 if (val & AHB_AXI_BUS_HALT_ACK)
293 break;
294
295 mdelay(1);
296 } while (time_before(jiffies, timeout));
297
298 if (!(val & AHB_AXI_BUS_HALT_ACK)) {
299 ath10k_err(ar, "failed to halt axi bus: %d\n", val);
300 return;
301 }
302
303 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n");
304 }
305
306 static void ath10k_ahb_halt_chip(struct ath10k *ar)
307 {
308 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
309 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg;
310 u32 val;
311 int ret;
312
313 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) ||
314 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
315 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
316 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
317 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
318 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
319 return;
320 }
321
322 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG);
323
324 switch (core_id) {
325 case 0:
326 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG;
327 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ;
328 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK;
329 break;
330 case 1:
331 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG;
332 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ;
333 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK;
334 break;
335 default:
336 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n",
337 core_id);
338 return;
339 }
340
341 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg);
342
343 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
344 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
345 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
346
347 ret = reset_control_assert(ar_ahb->core_cold_rst);
348 if (ret)
349 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);
350 msleep(1);
351
352 ret = reset_control_assert(ar_ahb->radio_cold_rst);
353 if (ret)
354 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);
355 msleep(1);
356
357 ret = reset_control_assert(ar_ahb->radio_warm_rst);
358 if (ret)
359 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);
360 msleep(1);
361
362 ret = reset_control_assert(ar_ahb->radio_srif_rst);
363 if (ret)
364 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);
365 msleep(1);
366
367 ret = reset_control_assert(ar_ahb->cpu_init_rst);
368 if (ret)
369 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);
370 msleep(10);
371
372
373
374
375 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
376 val &= ~AHB_AXI_BUS_HALT_REQ;
377 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
378
379 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
380 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
381 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
382
383 ret = reset_control_deassert(ar_ahb->core_cold_rst);
384 if (ret)
385 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);
386
387 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id);
388 }
389
390 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg)
391 {
392 struct ath10k *ar = arg;
393
394 if (!ath10k_pci_irq_pending(ar))
395 return IRQ_NONE;
396
397 ath10k_pci_disable_and_clear_legacy_irq(ar);
398 ath10k_pci_irq_msi_fw_mask(ar);
399 napi_schedule(&ar->napi);
400
401 return IRQ_HANDLED;
402 }
403
404 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar)
405 {
406 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
407 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
408 int ret;
409
410 ret = request_irq(ar_ahb->irq,
411 ath10k_ahb_interrupt_handler,
412 IRQF_SHARED, "ath10k_ahb", ar);
413 if (ret) {
414 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
415 ar_ahb->irq, ret);
416 return ret;
417 }
418 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
419
420 return 0;
421 }
422
423 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar)
424 {
425 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
426
427 free_irq(ar_ahb->irq, ar);
428 }
429
430 static void ath10k_ahb_irq_disable(struct ath10k *ar)
431 {
432 ath10k_ce_disable_interrupts(ar);
433 ath10k_pci_disable_and_clear_legacy_irq(ar);
434 }
435
436 static int ath10k_ahb_resource_init(struct ath10k *ar)
437 {
438 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
439 struct platform_device *pdev;
440 struct resource *res;
441 int ret;
442
443 pdev = ar_ahb->pdev;
444
445 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
446 if (!res) {
447 ath10k_err(ar, "failed to get memory resource\n");
448 ret = -ENXIO;
449 goto out;
450 }
451
452 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res);
453 if (IS_ERR(ar_ahb->mem)) {
454 ath10k_err(ar, "mem ioremap error\n");
455 ret = PTR_ERR(ar_ahb->mem);
456 goto out;
457 }
458
459 ar_ahb->mem_len = resource_size(res);
460
461 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE,
462 ATH10K_GCC_REG_SIZE);
463 if (!ar_ahb->gcc_mem) {
464 ath10k_err(ar, "gcc mem ioremap error\n");
465 ret = -ENOMEM;
466 goto err_mem_unmap;
467 }
468
469 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE,
470 ATH10K_TCSR_REG_SIZE);
471 if (!ar_ahb->tcsr_mem) {
472 ath10k_err(ar, "tcsr mem ioremap error\n");
473 ret = -ENOMEM;
474 goto err_gcc_mem_unmap;
475 }
476
477 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
478 if (ret) {
479 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);
480 goto err_tcsr_mem_unmap;
481 }
482
483 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
484 if (ret) {
485 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n",
486 ret);
487 goto err_tcsr_mem_unmap;
488 }
489
490 ret = ath10k_ahb_clock_init(ar);
491 if (ret)
492 goto err_tcsr_mem_unmap;
493
494 ret = ath10k_ahb_rst_ctrl_init(ar);
495 if (ret)
496 goto err_clock_deinit;
497
498 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy");
499 if (ar_ahb->irq < 0) {
500 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq);
501 ret = ar_ahb->irq;
502 goto err_clock_deinit;
503 }
504
505 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq);
506
507 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n",
508 ar_ahb->mem, ar_ahb->mem_len,
509 ar_ahb->gcc_mem, ar_ahb->tcsr_mem);
510 return 0;
511
512 err_clock_deinit:
513 ath10k_ahb_clock_deinit(ar);
514
515 err_tcsr_mem_unmap:
516 iounmap(ar_ahb->tcsr_mem);
517
518 err_gcc_mem_unmap:
519 ar_ahb->tcsr_mem = NULL;
520 iounmap(ar_ahb->gcc_mem);
521
522 err_mem_unmap:
523 ar_ahb->gcc_mem = NULL;
524 devm_iounmap(&pdev->dev, ar_ahb->mem);
525
526 out:
527 ar_ahb->mem = NULL;
528 return ret;
529 }
530
531 static void ath10k_ahb_resource_deinit(struct ath10k *ar)
532 {
533 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
534 struct device *dev;
535
536 dev = &ar_ahb->pdev->dev;
537
538 if (ar_ahb->mem)
539 devm_iounmap(dev, ar_ahb->mem);
540
541 if (ar_ahb->gcc_mem)
542 iounmap(ar_ahb->gcc_mem);
543
544 if (ar_ahb->tcsr_mem)
545 iounmap(ar_ahb->tcsr_mem);
546
547 ar_ahb->mem = NULL;
548 ar_ahb->gcc_mem = NULL;
549 ar_ahb->tcsr_mem = NULL;
550
551 ath10k_ahb_clock_deinit(ar);
552 ath10k_ahb_rst_ctrl_deinit(ar);
553 }
554
555 static int ath10k_ahb_prepare_device(struct ath10k *ar)
556 {
557 u32 val;
558 int ret;
559
560 ret = ath10k_ahb_clock_enable(ar);
561 if (ret) {
562 ath10k_err(ar, "failed to enable clocks\n");
563 return ret;
564 }
565
566
567
568
569
570
571
572
573 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV);
574 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val);
575
576 ret = ath10k_ahb_release_reset(ar);
577 if (ret)
578 goto err_clk_disable;
579
580 ath10k_ahb_irq_disable(ar);
581
582 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
583
584 ret = ath10k_pci_wait_for_target_init(ar);
585 if (ret)
586 goto err_halt_chip;
587
588 return 0;
589
590 err_halt_chip:
591 ath10k_ahb_halt_chip(ar);
592
593 err_clk_disable:
594 ath10k_ahb_clock_disable(ar);
595
596 return ret;
597 }
598
599 static int ath10k_ahb_chip_reset(struct ath10k *ar)
600 {
601 int ret;
602
603 ath10k_ahb_halt_chip(ar);
604 ath10k_ahb_clock_disable(ar);
605
606 ret = ath10k_ahb_prepare_device(ar);
607 if (ret)
608 return ret;
609
610 return 0;
611 }
612
613 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar)
614 {
615 u32 addr, val;
616
617 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
618 val = ath10k_ahb_read32(ar, addr);
619 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK;
620 ath10k_ahb_write32(ar, addr, val);
621
622 return 0;
623 }
624
625 static int ath10k_ahb_hif_start(struct ath10k *ar)
626 {
627 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n");
628
629 napi_enable(&ar->napi);
630 ath10k_ce_enable_interrupts(ar);
631 ath10k_pci_enable_legacy_irq(ar);
632
633 ath10k_pci_rx_post(ar);
634
635 return 0;
636 }
637
638 static void ath10k_ahb_hif_stop(struct ath10k *ar)
639 {
640 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
641
642 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n");
643
644 ath10k_ahb_irq_disable(ar);
645 synchronize_irq(ar_ahb->irq);
646
647 napi_synchronize(&ar->napi);
648 napi_disable(&ar->napi);
649
650 ath10k_pci_flush(ar);
651 }
652
653 static int ath10k_ahb_hif_power_up(struct ath10k *ar,
654 enum ath10k_firmware_mode fw_mode)
655 {
656 int ret;
657
658 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n");
659
660 ret = ath10k_ahb_chip_reset(ar);
661 if (ret) {
662 ath10k_err(ar, "failed to reset chip: %d\n", ret);
663 goto out;
664 }
665
666 ret = ath10k_pci_init_pipes(ar);
667 if (ret) {
668 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
669 goto out;
670 }
671
672 ret = ath10k_pci_init_config(ar);
673 if (ret) {
674 ath10k_err(ar, "failed to setup init config: %d\n", ret);
675 goto err_ce_deinit;
676 }
677
678 ret = ath10k_ahb_wake_target_cpu(ar);
679 if (ret) {
680 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
681 goto err_ce_deinit;
682 }
683
684 return 0;
685
686 err_ce_deinit:
687 ath10k_pci_ce_deinit(ar);
688 out:
689 return ret;
690 }
691
692 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
693 {
694 u32 val = 0, region = addr & 0xfffff;
695
696 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
697
698 if (region >= QCA4019_SRAM_ADDR && region <=
699 (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) {
700
701
702
703 val |= region;
704 } else {
705 val |= 0x100000 | region;
706 }
707
708 return val;
709 }
710
711 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = {
712 .tx_sg = ath10k_pci_hif_tx_sg,
713 .diag_read = ath10k_pci_hif_diag_read,
714 .diag_write = ath10k_pci_diag_write_mem,
715 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
716 .start = ath10k_ahb_hif_start,
717 .stop = ath10k_ahb_hif_stop,
718 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
719 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
720 .send_complete_check = ath10k_pci_hif_send_complete_check,
721 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
722 .power_up = ath10k_ahb_hif_power_up,
723 .power_down = ath10k_pci_hif_power_down,
724 .read32 = ath10k_ahb_read32,
725 .write32 = ath10k_ahb_write32,
726 };
727
728 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = {
729 .read32 = ath10k_ahb_read32,
730 .write32 = ath10k_ahb_write32,
731 .get_num_banks = ath10k_ahb_get_num_banks,
732 };
733
734 static int ath10k_ahb_probe(struct platform_device *pdev)
735 {
736 struct ath10k *ar;
737 struct ath10k_ahb *ar_ahb;
738 struct ath10k_pci *ar_pci;
739 const struct of_device_id *of_id;
740 enum ath10k_hw_rev hw_rev;
741 size_t size;
742 int ret;
743 struct ath10k_bus_params bus_params = {};
744
745 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev);
746 if (!of_id) {
747 dev_err(&pdev->dev, "failed to find matching device tree id\n");
748 return -EINVAL;
749 }
750
751 hw_rev = (enum ath10k_hw_rev)of_id->data;
752
753 size = sizeof(*ar_pci) + sizeof(*ar_ahb);
754 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,
755 hw_rev, &ath10k_ahb_hif_ops);
756 if (!ar) {
757 dev_err(&pdev->dev, "failed to allocate core\n");
758 return -ENOMEM;
759 }
760
761 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n");
762
763 ar_pci = ath10k_pci_priv(ar);
764 ar_ahb = ath10k_ahb_priv(ar);
765
766 ar_ahb->pdev = pdev;
767 platform_set_drvdata(pdev, ar);
768
769 ret = ath10k_ahb_resource_init(ar);
770 if (ret)
771 goto err_core_destroy;
772
773 ar->dev_id = 0;
774 ar_pci->mem = ar_ahb->mem;
775 ar_pci->mem_len = ar_ahb->mem_len;
776 ar_pci->ar = ar;
777 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops;
778 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr;
779 ar->ce_priv = &ar_pci->ce;
780
781 ret = ath10k_pci_setup_resource(ar);
782 if (ret) {
783 ath10k_err(ar, "failed to setup resource: %d\n", ret);
784 goto err_resource_deinit;
785 }
786
787 ath10k_pci_init_napi(ar);
788
789 ret = ath10k_ahb_request_irq_legacy(ar);
790 if (ret)
791 goto err_free_pipes;
792
793 ret = ath10k_ahb_prepare_device(ar);
794 if (ret)
795 goto err_free_irq;
796
797 ath10k_pci_ce_deinit(ar);
798
799 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
800 bus_params.chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
801 if (bus_params.chip_id == 0xffffffff) {
802 ath10k_err(ar, "failed to get chip id\n");
803 ret = -ENODEV;
804 goto err_halt_device;
805 }
806
807 ret = ath10k_core_register(ar, &bus_params);
808 if (ret) {
809 ath10k_err(ar, "failed to register driver core: %d\n", ret);
810 goto err_halt_device;
811 }
812
813 return 0;
814
815 err_halt_device:
816 ath10k_ahb_halt_chip(ar);
817 ath10k_ahb_clock_disable(ar);
818
819 err_free_irq:
820 ath10k_ahb_release_irq_legacy(ar);
821
822 err_free_pipes:
823 ath10k_pci_free_pipes(ar);
824
825 err_resource_deinit:
826 ath10k_ahb_resource_deinit(ar);
827
828 err_core_destroy:
829 ath10k_core_destroy(ar);
830 platform_set_drvdata(pdev, NULL);
831
832 return ret;
833 }
834
835 static int ath10k_ahb_remove(struct platform_device *pdev)
836 {
837 struct ath10k *ar = platform_get_drvdata(pdev);
838 struct ath10k_ahb *ar_ahb;
839
840 if (!ar)
841 return -EINVAL;
842
843 ar_ahb = ath10k_ahb_priv(ar);
844
845 if (!ar_ahb)
846 return -EINVAL;
847
848 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");
849
850 ath10k_core_unregister(ar);
851 ath10k_ahb_irq_disable(ar);
852 ath10k_ahb_release_irq_legacy(ar);
853 ath10k_pci_release_resource(ar);
854 ath10k_ahb_halt_chip(ar);
855 ath10k_ahb_clock_disable(ar);
856 ath10k_ahb_resource_deinit(ar);
857 ath10k_core_destroy(ar);
858
859 platform_set_drvdata(pdev, NULL);
860
861 return 0;
862 }
863
864 static struct platform_driver ath10k_ahb_driver = {
865 .driver = {
866 .name = "ath10k_ahb",
867 .of_match_table = ath10k_ahb_of_match,
868 },
869 .probe = ath10k_ahb_probe,
870 .remove = ath10k_ahb_remove,
871 };
872
873 int ath10k_ahb_init(void)
874 {
875 int ret;
876
877 ret = platform_driver_register(&ath10k_ahb_driver);
878 if (ret)
879 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n",
880 ret);
881 return ret;
882 }
883
884 void ath10k_ahb_exit(void)
885 {
886 platform_driver_unregister(&ath10k_ahb_driver);
887 }