This source file includes following definitions.
- ath9k_hw_common
- ath9k_hw_regulatory
- ath9k_hw_private_ops
- ath9k_hw_ops
- get_streams
- ath9k_hw_btcoex_is_enabled
- ath9k_hw_mci_is_enabled
- ath9k_hw_get_btcoex_scheme
- ar9003_hw_attach_aic_ops
- ath9k_hw_btcoex_is_enabled
- ath9k_hw_mci_is_enabled
- ath9k_hw_btcoex_enable
- ath9k_hw_get_btcoex_scheme
- ath9k_hw_wow_apply_pattern
- ath9k_hw_wow_wakeup
- ath9k_hw_wow_enable
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17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/firmware.h>
24
25 #include "mac.h"
26 #include "ani.h"
27 #include "eeprom.h"
28 #include "calib.h"
29 #include "reg.h"
30 #include "reg_mci.h"
31 #include "phy.h"
32 #include "btcoex.h"
33 #include "dynack.h"
34
35 #include "../regd.h"
36
37 #define ATHEROS_VENDOR_ID 0x168c
38
39 #define AR5416_DEVID_PCI 0x0023
40 #define AR5416_DEVID_PCIE 0x0024
41 #define AR9160_DEVID_PCI 0x0027
42 #define AR9280_DEVID_PCI 0x0029
43 #define AR9280_DEVID_PCIE 0x002a
44 #define AR9285_DEVID_PCIE 0x002b
45 #define AR2427_DEVID_PCIE 0x002c
46 #define AR9287_DEVID_PCI 0x002d
47 #define AR9287_DEVID_PCIE 0x002e
48 #define AR9300_DEVID_PCIE 0x0030
49 #define AR9300_DEVID_AR9340 0x0031
50 #define AR9300_DEVID_AR9485_PCIE 0x0032
51 #define AR9300_DEVID_AR9580 0x0033
52 #define AR9300_DEVID_AR9462 0x0034
53 #define AR9300_DEVID_AR9330 0x0035
54 #define AR9300_DEVID_QCA955X 0x0038
55 #define AR9485_DEVID_AR1111 0x0037
56 #define AR9300_DEVID_AR9565 0x0036
57 #define AR9300_DEVID_AR953X 0x003d
58 #define AR9300_DEVID_QCA956X 0x003f
59
60 #define AR5416_AR9100_DEVID 0x000b
61
62 #define AR_SUBVENDOR_ID_NOG 0x0e11
63 #define AR_SUBVENDOR_ID_NEW_A 0x7065
64 #define AR5416_MAGIC 0x19641014
65
66 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
67 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
68 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
69
70 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
71
72 #define ATH_DEFAULT_NOISE_FLOOR -95
73
74 #define ATH9K_RSSI_BAD -128
75
76 #define ATH9K_NUM_CHANNELS 38
77
78
79 #define REG_WRITE(_ah, _reg, _val) \
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
81
82 #define REG_READ(_ah, _reg) \
83 (_ah)->reg_ops.read((_ah), (_reg))
84
85 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
87
88 #define REG_RMW(_ah, _reg, _set, _clr) \
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
90
91 #define ENABLE_REGWRITE_BUFFER(_ah) \
92 do { \
93 if ((_ah)->reg_ops.enable_write_buffer) \
94 (_ah)->reg_ops.enable_write_buffer((_ah)); \
95 } while (0)
96
97 #define REGWRITE_BUFFER_FLUSH(_ah) \
98 do { \
99 if ((_ah)->reg_ops.write_flush) \
100 (_ah)->reg_ops.write_flush((_ah)); \
101 } while (0)
102
103 #define ENABLE_REG_RMW_BUFFER(_ah) \
104 do { \
105 if ((_ah)->reg_ops.enable_rmw_buffer) \
106 (_ah)->reg_ops.enable_rmw_buffer((_ah)); \
107 } while (0)
108
109 #define REG_RMW_BUFFER_FLUSH(_ah) \
110 do { \
111 if ((_ah)->reg_ops.rmw_flush) \
112 (_ah)->reg_ops.rmw_flush((_ah)); \
113 } while (0)
114
115 #define PR_EEP(_s, _val) \
116 do { \
117 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
118 _s, (_val)); \
119 } while (0)
120
121 #define SM(_v, _f) (((_v) << _f##_S) & _f)
122 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
123 #define REG_RMW_FIELD(_a, _r, _f, _v) \
124 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
125 #define REG_READ_FIELD(_a, _r, _f) \
126 (((REG_READ(_a, _r) & _f) >> _f##_S))
127 #define REG_SET_BIT(_a, _r, _f) \
128 REG_RMW(_a, _r, (_f), 0)
129 #define REG_CLR_BIT(_a, _r, _f) \
130 REG_RMW(_a, _r, 0, (_f))
131
132 #define DO_DELAY(x) do { \
133 if (((++(x) % 64) == 0) && \
134 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
135 != ATH_USB)) \
136 udelay(1); \
137 } while (0)
138
139 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
140 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
141 #define REG_READ_ARRAY(ah, array, size) \
142 ath9k_hw_read_array(ah, array, size)
143
144 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
145 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
146 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
147 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
148 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
149 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
150 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
151 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
152 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
153 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
154 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
155 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
156 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
157 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
158 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
159 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
160 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
161
162 #define AR_GPIOD_MASK 0x00001FFF
163
164 #define BASE_ACTIVATE_DELAY 100
165 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
166 #define COEF_SCALE_S 24
167 #define HT40_CHANNEL_CENTER_SHIFT 10
168
169 #define ATH9K_ANTENNA0_CHAINMASK 0x1
170 #define ATH9K_ANTENNA1_CHAINMASK 0x2
171
172 #define ATH9K_NUM_DMA_DEBUG_REGS 8
173 #define ATH9K_NUM_QUEUES 10
174
175 #define MAX_RATE_POWER 63
176 #define MAX_COMBINED_POWER 254
177 #define AH_WAIT_TIMEOUT 100000
178 #define AH_TSF_WRITE_TIMEOUT 100
179 #define AH_TIME_QUANTUM 10
180 #define AR_KEYTABLE_SIZE 128
181 #define POWER_UP_TIME 10000
182 #define SPUR_RSSI_THRESH 40
183 #define UPPER_5G_SUB_BAND_START 5700
184 #define MID_5G_SUB_BAND_START 5400
185
186 #define CAB_TIMEOUT_VAL 10
187 #define BEACON_TIMEOUT_VAL 10
188 #define MIN_BEACON_TIMEOUT_VAL 1
189 #define SLEEP_SLOP TU_TO_USEC(3)
190
191 #define INIT_CONFIG_STATUS 0x00000000
192 #define INIT_RSSI_THR 0x00000700
193 #define INIT_BCON_CNTRL_REG 0x00000000
194
195 #define TU_TO_USEC(_tu) ((_tu) << 10)
196
197 #define ATH9K_HW_RX_HP_QDEPTH 16
198 #define ATH9K_HW_RX_LP_QDEPTH 128
199
200 #define PAPRD_GAIN_TABLE_ENTRIES 32
201 #define PAPRD_TABLE_SZ 24
202 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
203
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208
209 #define KAL_FRAME_LEN 28
210 #define KAL_FRAME_TYPE 0x2
211 #define KAL_FRAME_SUB_TYPE 0x4
212 #define KAL_DURATION_ID 0x3d
213 #define KAL_NUM_DATA_WORDS 6
214 #define KAL_NUM_DESC_WORDS 12
215 #define KAL_ANTENNA_MODE 1
216 #define KAL_TO_DS 1
217 #define KAL_DELAY 4
218 #define KAL_TIMEOUT 900
219
220 #define MAX_PATTERN_SIZE 256
221 #define MAX_PATTERN_MASK_SIZE 32
222 #define MAX_NUM_PATTERN 16
223 #define MAX_NUM_PATTERN_LEGACY 8
224 #define MAX_NUM_USER_PATTERN 6
225
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230
231 #define AH_WOW_USER_PATTERN_EN BIT(0)
232 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
233 #define AH_WOW_LINK_CHANGE BIT(2)
234 #define AH_WOW_BEACON_MISS BIT(3)
235
236 enum ath_hw_txq_subtype {
237 ATH_TXQ_AC_BK = 0,
238 ATH_TXQ_AC_BE = 1,
239 ATH_TXQ_AC_VI = 2,
240 ATH_TXQ_AC_VO = 3,
241 };
242
243 enum ath_ini_subsys {
244 ATH_INI_PRE = 0,
245 ATH_INI_CORE,
246 ATH_INI_POST,
247 ATH_INI_NUM_SPLIT,
248 };
249
250 enum ath9k_hw_caps {
251 ATH9K_HW_CAP_HT = BIT(0),
252 ATH9K_HW_CAP_RFSILENT = BIT(1),
253 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
254 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
255 ATH9K_HW_CAP_EDMA = BIT(4),
256 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
257 ATH9K_HW_CAP_LDPC = BIT(6),
258 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
259 ATH9K_HW_CAP_SGI_20 = BIT(8),
260 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
261 ATH9K_HW_CAP_2GHZ = BIT(11),
262 ATH9K_HW_CAP_5GHZ = BIT(12),
263 ATH9K_HW_CAP_APM = BIT(13),
264 #ifdef CONFIG_ATH9K_PCOEM
265 ATH9K_HW_CAP_RTT = BIT(14),
266 ATH9K_HW_CAP_MCI = BIT(15),
267 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17),
268 #else
269 ATH9K_HW_CAP_RTT = 0,
270 ATH9K_HW_CAP_MCI = 0,
271 ATH9K_HW_CAP_BT_ANT_DIV = 0,
272 #endif
273 ATH9K_HW_CAP_DFS = BIT(18),
274 ATH9K_HW_CAP_PAPRD = BIT(19),
275 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20),
276 };
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288
289 struct ath9k_hw_wow {
290 u32 wow_event_mask;
291 u32 wow_event_mask2;
292 u8 max_patterns;
293 };
294
295 struct ath9k_hw_capabilities {
296 u32 hw_caps;
297 u16 rts_aggr_limit;
298 u8 tx_chainmask;
299 u8 rx_chainmask;
300 u8 chip_chainmask;
301 u8 max_txchains;
302 u8 max_rxchains;
303 u8 num_gpio_pins;
304 u32 gpio_mask;
305 u32 gpio_requested;
306 u8 rx_hp_qdepth;
307 u8 rx_lp_qdepth;
308 u8 rx_status_len;
309 u8 tx_desc_len;
310 u8 txs_len;
311 };
312
313 #define AR_NO_SPUR 0x8000
314 #define AR_BASE_FREQ_2GHZ 2300
315 #define AR_BASE_FREQ_5GHZ 4900
316 #define AR_SPUR_FEEQ_BOUND_HT40 19
317 #define AR_SPUR_FEEQ_BOUND_HT20 10
318
319 enum ath9k_hw_hang_checks {
320 HW_BB_WATCHDOG = BIT(0),
321 HW_PHYRESTART_CLC_WAR = BIT(1),
322 HW_BB_RIFS_HANG = BIT(2),
323 HW_BB_DFS_HANG = BIT(3),
324 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
325 HW_MAC_HANG = BIT(5),
326 };
327
328 #define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0)
329 #define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1)
330 #define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2)
331 #define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3)
332 #define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4)
333
334 struct ath9k_ops_config {
335 int dma_beacon_response_time;
336 int sw_beacon_response_time;
337 bool cwm_ignore_extcca;
338 u32 pcie_waen;
339 u8 analog_shiftreg;
340 u32 ofdm_trig_low;
341 u32 ofdm_trig_high;
342 u32 cck_trig_high;
343 u32 cck_trig_low;
344 bool enable_paprd;
345 int serialize_regmode;
346 bool rx_intr_mitigation;
347 bool tx_intr_mitigation;
348 u8 max_txtrig_level;
349 u16 ani_poll_interval;
350 u16 hw_hang_checks;
351 u16 rimt_first;
352 u16 rimt_last;
353
354
355 u32 aspm_l1_fix;
356 u32 xlna_gpio;
357 u32 ant_ctrl_comm2g_switch_enable;
358 bool xatten_margin_cfg;
359 bool alt_mingainidx;
360 u8 pll_pwrsave;
361 bool tx_gain_buffalo;
362 bool led_active_high;
363 };
364
365 enum ath9k_int {
366 ATH9K_INT_RX = 0x00000001,
367 ATH9K_INT_RXDESC = 0x00000002,
368 ATH9K_INT_RXHP = 0x00000001,
369 ATH9K_INT_RXLP = 0x00000002,
370 ATH9K_INT_RXNOFRM = 0x00000008,
371 ATH9K_INT_RXEOL = 0x00000010,
372 ATH9K_INT_RXORN = 0x00000020,
373 ATH9K_INT_TX = 0x00000040,
374 ATH9K_INT_TXDESC = 0x00000080,
375 ATH9K_INT_TIM_TIMER = 0x00000100,
376 ATH9K_INT_MCI = 0x00000200,
377 ATH9K_INT_BB_WATCHDOG = 0x00000400,
378 ATH9K_INT_TXURN = 0x00000800,
379 ATH9K_INT_MIB = 0x00001000,
380 ATH9K_INT_RXPHY = 0x00004000,
381 ATH9K_INT_RXKCM = 0x00008000,
382 ATH9K_INT_SWBA = 0x00010000,
383 ATH9K_INT_BMISS = 0x00040000,
384 ATH9K_INT_BNR = 0x00100000,
385 ATH9K_INT_TIM = 0x00200000,
386 ATH9K_INT_DTIM = 0x00400000,
387 ATH9K_INT_DTIMSYNC = 0x00800000,
388 ATH9K_INT_GPIO = 0x01000000,
389 ATH9K_INT_CABEND = 0x02000000,
390 ATH9K_INT_TSFOOR = 0x04000000,
391 ATH9K_INT_GENTIMER = 0x08000000,
392 ATH9K_INT_CST = 0x10000000,
393 ATH9K_INT_GTT = 0x20000000,
394 ATH9K_INT_FATAL = 0x40000000,
395 ATH9K_INT_GLOBAL = 0x80000000,
396 ATH9K_INT_BMISC = ATH9K_INT_TIM |
397 ATH9K_INT_DTIM |
398 ATH9K_INT_DTIMSYNC |
399 ATH9K_INT_TSFOOR |
400 ATH9K_INT_CABEND,
401 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
402 ATH9K_INT_RXDESC |
403 ATH9K_INT_RXEOL |
404 ATH9K_INT_RXORN |
405 ATH9K_INT_TXURN |
406 ATH9K_INT_TXDESC |
407 ATH9K_INT_MIB |
408 ATH9K_INT_RXPHY |
409 ATH9K_INT_RXKCM |
410 ATH9K_INT_SWBA |
411 ATH9K_INT_BMISS |
412 ATH9K_INT_GPIO,
413 ATH9K_INT_NOCARD = 0xffffffff
414 };
415
416 #define MAX_RTT_TABLE_ENTRY 6
417 #define MAX_IQCAL_MEASUREMENT 8
418 #define MAX_CL_TAB_ENTRY 16
419 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
420
421 enum ath9k_cal_flags {
422 RTT_DONE,
423 PAPRD_PACKET_SENT,
424 PAPRD_DONE,
425 NFCAL_PENDING,
426 NFCAL_INTF,
427 TXIQCAL_DONE,
428 TXCLCAL_DONE,
429 SW_PKDET_DONE,
430 };
431
432 struct ath9k_hw_cal_data {
433 u16 channel;
434 u16 channelFlags;
435 unsigned long cal_flags;
436 int32_t CalValid;
437 int8_t iCoff;
438 int8_t qCoff;
439 u8 caldac[2];
440 u16 small_signal_gain[AR9300_MAX_CHAINS];
441 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
442 u32 num_measures[AR9300_MAX_CHAINS];
443 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
444 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
445 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
446 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
447 };
448
449 struct ath9k_channel {
450 struct ieee80211_channel *chan;
451 u16 channel;
452 u16 channelFlags;
453 s16 noisefloor;
454 };
455
456 #define CHANNEL_5GHZ BIT(0)
457 #define CHANNEL_HALF BIT(1)
458 #define CHANNEL_QUARTER BIT(2)
459 #define CHANNEL_HT BIT(3)
460 #define CHANNEL_HT40PLUS BIT(4)
461 #define CHANNEL_HT40MINUS BIT(5)
462
463 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
464 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
465
466 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
467 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
468 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
469 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
470
471 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
472
473 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
474
475 #define IS_CHAN_HT40(_c) \
476 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
477
478 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
479 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
480
481 enum ath9k_power_mode {
482 ATH9K_PM_AWAKE = 0,
483 ATH9K_PM_FULL_SLEEP,
484 ATH9K_PM_NETWORK_SLEEP,
485 ATH9K_PM_UNDEFINED
486 };
487
488 enum ser_reg_mode {
489 SER_REG_MODE_OFF = 0,
490 SER_REG_MODE_ON = 1,
491 SER_REG_MODE_AUTO = 2,
492 };
493
494 enum ath9k_rx_qtype {
495 ATH9K_RX_QUEUE_HP,
496 ATH9K_RX_QUEUE_LP,
497 ATH9K_RX_QUEUE_MAX,
498 };
499
500 struct ath9k_beacon_state {
501 u32 bs_nexttbtt;
502 u32 bs_nextdtim;
503 u32 bs_intval;
504 #define ATH9K_TSFOOR_THRESHOLD 0x00004240
505 u32 bs_dtimperiod;
506 u16 bs_bmissthreshold;
507 u32 bs_sleepduration;
508 u32 bs_tsfoor_threshold;
509 };
510
511 struct chan_centers {
512 u16 synth_center;
513 u16 ctl_center;
514 u16 ext_center;
515 };
516
517 enum {
518 ATH9K_RESET_POWER_ON,
519 ATH9K_RESET_WARM,
520 ATH9K_RESET_COLD,
521 };
522
523 struct ath9k_hw_version {
524 u32 magic;
525 u16 devid;
526 u16 subvendorid;
527 u32 macVersion;
528 u16 macRev;
529 u16 phyRev;
530 u16 analog5GhzRev;
531 u16 analog2GhzRev;
532 enum ath_usb_dev usbdev;
533 };
534
535
536
537 #define ATH_MAX_GEN_TIMER 16
538
539 #define AR_GENTMR_BIT(_index) (1 << (_index))
540
541 struct ath_gen_timer_configuration {
542 u32 next_addr;
543 u32 period_addr;
544 u32 mode_addr;
545 u32 mode_mask;
546 };
547
548 struct ath_gen_timer {
549 void (*trigger)(void *arg);
550 void (*overflow)(void *arg);
551 void *arg;
552 u8 index;
553 };
554
555 struct ath_gen_timer_table {
556 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
557 u16 timer_mask;
558 bool tsf2_enabled;
559 };
560
561 struct ath_hw_antcomb_conf {
562 u8 main_lna_conf;
563 u8 alt_lna_conf;
564 u8 fast_div_bias;
565 u8 main_gaintb;
566 u8 alt_gaintb;
567 int lna1_lna2_delta;
568 int lna1_lna2_switch_delta;
569 u8 div_group;
570 };
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592 struct ath_hw_radar_conf {
593 unsigned int pulse_inband;
594 unsigned int pulse_inband_step;
595 unsigned int pulse_height;
596 unsigned int pulse_rssi;
597 unsigned int pulse_maxlen;
598
599 unsigned int radar_rssi;
600 unsigned int radar_inband;
601 int fir_power;
602
603 bool ext_channel;
604 };
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628 struct ath_hw_private_ops {
629 void (*init_hang_checks)(struct ath_hw *ah);
630 bool (*detect_mac_hang)(struct ath_hw *ah);
631 bool (*detect_bb_hang)(struct ath_hw *ah);
632
633
634 void (*init_cal_settings)(struct ath_hw *ah);
635 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
636
637 void (*init_mode_gain_regs)(struct ath_hw *ah);
638 void (*setup_calibration)(struct ath_hw *ah,
639 struct ath9k_cal_list *currCal);
640
641
642 int (*rf_set_freq)(struct ath_hw *ah,
643 struct ath9k_channel *chan);
644 void (*spur_mitigate_freq)(struct ath_hw *ah,
645 struct ath9k_channel *chan);
646 bool (*set_rf_regs)(struct ath_hw *ah,
647 struct ath9k_channel *chan,
648 u16 modesIndex);
649 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
650 void (*init_bb)(struct ath_hw *ah,
651 struct ath9k_channel *chan);
652 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
653 void (*olc_init)(struct ath_hw *ah);
654 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
655 void (*mark_phy_inactive)(struct ath_hw *ah);
656 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
657 bool (*rfbus_req)(struct ath_hw *ah);
658 void (*rfbus_done)(struct ath_hw *ah);
659 void (*restore_chainmask)(struct ath_hw *ah);
660 u32 (*compute_pll_control)(struct ath_hw *ah,
661 struct ath9k_channel *chan);
662 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
663 int param);
664 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
665 void (*set_radar_params)(struct ath_hw *ah,
666 struct ath_hw_radar_conf *conf);
667 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
668 u8 *ini_reloaded);
669
670
671 void (*ani_cache_ini_regs)(struct ath_hw *ah);
672
673 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
674 bool (*is_aic_enabled)(struct ath_hw *ah);
675 #endif
676 };
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700 struct ath_spec_scan {
701 bool enabled;
702 bool short_repeat;
703 bool endless;
704 u8 count;
705 u8 period;
706 u8 fft_period;
707 };
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722 struct ath_hw_ops {
723 void (*config_pci_powersave)(struct ath_hw *ah,
724 bool power_off);
725 void (*rx_enable)(struct ath_hw *ah);
726 void (*set_desc_link)(void *ds, u32 link);
727 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan,
728 u8 rxchainmask, bool longcal);
729 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
730 u32 *sync_cause_p);
731 void (*set_txdesc)(struct ath_hw *ah, void *ds,
732 struct ath_tx_info *i);
733 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
734 struct ath_tx_status *ts);
735 int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
736 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
737 struct ath_hw_antcomb_conf *antconf);
738 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
739 struct ath_hw_antcomb_conf *antconf);
740 void (*spectral_scan_config)(struct ath_hw *ah,
741 struct ath_spec_scan *param);
742 void (*spectral_scan_trigger)(struct ath_hw *ah);
743 void (*spectral_scan_wait)(struct ath_hw *ah);
744
745 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
746 void (*tx99_stop)(struct ath_hw *ah);
747 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
748
749 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
750 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
751 #endif
752 };
753
754 struct ath_nf_limits {
755 s16 max;
756 s16 min;
757 s16 nominal;
758 s16 cal[AR5416_MAX_CHAINS];
759 s16 pwr[AR5416_MAX_CHAINS];
760 };
761
762 enum ath_cal_list {
763 TX_IQ_CAL = BIT(0),
764 TX_IQ_ON_AGC_CAL = BIT(1),
765 TX_CL_CAL = BIT(2),
766 };
767
768
769 #define AH_USE_EEPROM 0x1
770 #define AH_UNPLUGGED 0x2
771 #define AH_FASTCC 0x4
772 #define AH_NO_EEP_SWAP 0x8
773
774 struct ath_hw {
775 struct ath_ops reg_ops;
776
777 struct device *dev;
778 struct ieee80211_hw *hw;
779 struct ath_common common;
780 struct ath9k_hw_version hw_version;
781 struct ath9k_ops_config config;
782 struct ath9k_hw_capabilities caps;
783 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
784 struct ath9k_channel *curchan;
785
786 union {
787 struct ar5416_eeprom_def def;
788 struct ar5416_eeprom_4k map4k;
789 struct ar9287_eeprom map9287;
790 struct ar9300_eeprom ar9300_eep;
791 } eeprom;
792 const struct eeprom_ops *eep_ops;
793
794 bool sw_mgmt_crypto_tx;
795 bool sw_mgmt_crypto_rx;
796 bool is_pciexpress;
797 bool aspm_enabled;
798 bool is_monitoring;
799 bool need_an_top2_fixup;
800 u16 tx_trig_level;
801
802 u32 nf_regs[6];
803 struct ath_nf_limits nf_2g;
804 struct ath_nf_limits nf_5g;
805 u16 rfsilent;
806 u32 rfkill_gpio;
807 u32 rfkill_polarity;
808 u32 ah_flags;
809 s16 nf_override;
810
811 bool reset_power_on;
812 bool htc_reset_init;
813
814 enum nl80211_iftype opmode;
815 enum ath9k_power_mode power_mode;
816
817 s8 noise;
818 struct ath9k_hw_cal_data *caldata;
819 struct ath9k_pacal_info pacal_info;
820 struct ar5416Stats stats;
821 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
822
823 enum ath9k_int imask;
824 u32 imrs2_reg;
825 u32 txok_interrupt_mask;
826 u32 txerr_interrupt_mask;
827 u32 txdesc_interrupt_mask;
828 u32 txeol_interrupt_mask;
829 u32 txurn_interrupt_mask;
830 atomic_t intr_ref_cnt;
831 bool chip_fullsleep;
832 u32 modes_index;
833
834
835 u32 supp_cals;
836 struct ath9k_cal_list iq_caldata;
837 struct ath9k_cal_list adcgain_caldata;
838 struct ath9k_cal_list adcdc_caldata;
839 struct ath9k_cal_list *cal_list;
840 struct ath9k_cal_list *cal_list_last;
841 struct ath9k_cal_list *cal_list_curr;
842 #define totalPowerMeasI meas0.unsign
843 #define totalPowerMeasQ meas1.unsign
844 #define totalIqCorrMeas meas2.sign
845 #define totalAdcIOddPhase meas0.unsign
846 #define totalAdcIEvenPhase meas1.unsign
847 #define totalAdcQOddPhase meas2.unsign
848 #define totalAdcQEvenPhase meas3.unsign
849 #define totalAdcDcOffsetIOddPhase meas0.sign
850 #define totalAdcDcOffsetIEvenPhase meas1.sign
851 #define totalAdcDcOffsetQOddPhase meas2.sign
852 #define totalAdcDcOffsetQEvenPhase meas3.sign
853 union {
854 u32 unsign[AR5416_MAX_CHAINS];
855 int32_t sign[AR5416_MAX_CHAINS];
856 } meas0;
857 union {
858 u32 unsign[AR5416_MAX_CHAINS];
859 int32_t sign[AR5416_MAX_CHAINS];
860 } meas1;
861 union {
862 u32 unsign[AR5416_MAX_CHAINS];
863 int32_t sign[AR5416_MAX_CHAINS];
864 } meas2;
865 union {
866 u32 unsign[AR5416_MAX_CHAINS];
867 int32_t sign[AR5416_MAX_CHAINS];
868 } meas3;
869 u16 cal_samples;
870 u8 enabled_cals;
871
872 u32 sta_id1_defaults;
873 u32 misc_mode;
874
875
876 struct ath_hw_private_ops private_ops;
877
878 struct ath_hw_ops ops;
879
880
881 u32 *analogBank6Data;
882
883 int coverage_class;
884 u32 slottime;
885 u32 globaltxtimeout;
886
887
888 u32 aniperiod;
889 enum ath9k_ani_cmd ani_function;
890 u32 ani_skip_count;
891 struct ar5416AniState ani;
892
893 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
894 struct ath_btcoex_hw btcoex_hw;
895 #endif
896
897 u32 intr_txqs;
898 u8 txchainmask;
899 u8 rxchainmask;
900
901 struct ath_hw_radar_conf radar_conf;
902
903 u32 originalGain[22];
904 int initPDADC;
905 int PDADCdelta;
906 int led_pin;
907 u32 gpio_mask;
908 u32 gpio_val;
909
910 struct ar5416IniArray ini_dfs;
911 struct ar5416IniArray iniModes;
912 struct ar5416IniArray iniCommon;
913 struct ar5416IniArray iniBB_RfGain;
914 struct ar5416IniArray iniBank6;
915 struct ar5416IniArray iniAddac;
916 struct ar5416IniArray iniPcieSerdes;
917 struct ar5416IniArray iniPcieSerdesLowPower;
918 struct ar5416IniArray iniModesFastClock;
919 struct ar5416IniArray iniAdditional;
920 struct ar5416IniArray iniModesRxGain;
921 struct ar5416IniArray ini_modes_rx_gain_bounds;
922 struct ar5416IniArray iniModesTxGain;
923 struct ar5416IniArray iniCckfirNormal;
924 struct ar5416IniArray iniCckfirJapan2484;
925 struct ar5416IniArray iniModes_9271_ANI_reg;
926 struct ar5416IniArray ini_radio_post_sys2ant;
927 struct ar5416IniArray ini_modes_rxgain_xlna;
928 struct ar5416IniArray ini_modes_rxgain_bb_core;
929 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
930
931 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
932 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
933 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
934 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
935
936 u32 intr_gen_timer_trigger;
937 u32 intr_gen_timer_thresh;
938 struct ath_gen_timer_table hw_gen_timers;
939
940 struct ar9003_txs *ts_ring;
941 u32 ts_paddr_start;
942 u32 ts_paddr_end;
943 u16 ts_tail;
944 u16 ts_size;
945
946 u32 bb_watchdog_last_status;
947 u32 bb_watchdog_timeout_ms;
948 u8 bb_hang_rx_ofdm;
949
950 unsigned int paprd_target_power;
951 unsigned int paprd_training_power;
952 unsigned int paprd_ratemask;
953 unsigned int paprd_ratemask_ht40;
954 bool paprd_table_write_done;
955 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
956 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
957
958
959
960
961
962 u32 WARegVal;
963
964
965 u32 ent_mode;
966
967 #ifdef CONFIG_ATH9K_WOW
968 struct ath9k_hw_wow wow;
969 #endif
970 bool is_clk_25mhz;
971 int (*get_mac_revision)(void);
972 int (*external_reset)(void);
973 bool disable_2ghz;
974 bool disable_5ghz;
975
976 const struct firmware *eeprom_blob;
977
978 struct ath_dynack dynack;
979
980 bool tpc_enabled;
981 u8 tx_power[Ar5416RateSize];
982 u8 tx_power_stbc[Ar5416RateSize];
983 bool msi_enabled;
984 u32 msi_mask;
985 u32 msi_reg;
986 };
987
988 struct ath_bus_ops {
989 enum ath_bus_type ath_bus_type;
990 void (*read_cachesize)(struct ath_common *common, int *csz);
991 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
992 void (*bt_coex_prep)(struct ath_common *common);
993 void (*aspm_init)(struct ath_common *common);
994 };
995
996 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
997 {
998 return &ah->common;
999 }
1000
1001 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
1002 {
1003 return &(ath9k_hw_common(ah)->regulatory);
1004 }
1005
1006 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
1007 {
1008 return &ah->private_ops;
1009 }
1010
1011 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
1012 {
1013 return &ah->ops;
1014 }
1015
1016 static inline u8 get_streams(int mask)
1017 {
1018 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
1019 }
1020
1021
1022 void ath9k_hw_deinit(struct ath_hw *ah);
1023 int ath9k_hw_init(struct ath_hw *ah);
1024 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1025 struct ath9k_hw_cal_data *caldata, bool fastcc);
1026 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
1027 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
1028
1029
1030 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label);
1031 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
1032 u32 ah_signal_type);
1033 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio);
1034 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
1035 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
1036 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1037
1038
1039 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
1040 int hw_delay);
1041 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1042 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
1043 int column, unsigned int *writecnt);
1044 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size);
1045 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1046 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1047 u8 phy, int kbps,
1048 u32 frameLen, u16 rateix, bool shortPreamble);
1049 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1050 struct ath9k_channel *chan,
1051 struct chan_centers *centers);
1052 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1053 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1054 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1055 bool ath9k_hw_disable(struct ath_hw *ah);
1056 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1057 void ath9k_hw_setopmode(struct ath_hw *ah);
1058 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1059 void ath9k_hw_write_associd(struct ath_hw *ah);
1060 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1061 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1062 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1063 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1064 u32 ath9k_hw_get_tsf_offset(struct timespec64 *last, struct timespec64 *cur);
1065 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1066 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1067 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1068 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1069 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1070 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1071 const struct ath9k_beacon_state *bs);
1072 void ath9k_hw_check_nav(struct ath_hw *ah);
1073 bool ath9k_hw_check_alive(struct ath_hw *ah);
1074
1075 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1076
1077
1078 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1079 void (*trigger)(void *),
1080 void (*overflow)(void *),
1081 void *arg,
1082 u8 timer_index);
1083 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1084 struct ath_gen_timer *timer,
1085 u32 timer_next,
1086 u32 timer_period);
1087 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah);
1088 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1089
1090 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1091 void ath_gen_timer_isr(struct ath_hw *hw);
1092
1093 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1094
1095
1096 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1097 u32 *coef_mantissa, u32 *coef_exponent);
1098 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1099 bool test);
1100
1101
1102
1103
1104
1105 int ar9002_hw_rf_claim(struct ath_hw *ah);
1106 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1107
1108
1109
1110
1111
1112 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1113 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1114 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1115 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1116 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1117 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1118 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1119 struct ath9k_hw_cal_data *caldata,
1120 int chain);
1121 int ar9003_paprd_create_curve(struct ath_hw *ah,
1122 struct ath9k_hw_cal_data *caldata, int chain);
1123 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1124 int ar9003_paprd_init_table(struct ath_hw *ah);
1125 bool ar9003_paprd_is_done(struct ath_hw *ah);
1126 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1127 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1128 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1129 struct ath9k_channel *chan);
1130 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
1131 struct ath9k_channel *chan, int bin);
1132 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1133 struct ath9k_channel *chan, int ht40_delta);
1134
1135
1136 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1137 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1138 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1139
1140 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1141 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1142
1143 int ar9002_hw_attach_ops(struct ath_hw *ah);
1144 void ar9003_hw_attach_ops(struct ath_hw *ah);
1145
1146 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1147
1148 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1149 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1150
1151 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1152 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1153 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1154
1155 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1156 void ar9003_hw_attach_aic_ops(struct ath_hw *ah);
1157 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1158 {
1159 return ah->btcoex_hw.enabled;
1160 }
1161 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1162 {
1163 return ah->common.btcoex_enabled &&
1164 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1165
1166 }
1167 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1168 static inline enum ath_btcoex_scheme
1169 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1170 {
1171 return ah->btcoex_hw.scheme;
1172 }
1173 #else
1174 static inline void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
1175 {
1176 }
1177 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1178 {
1179 return false;
1180 }
1181 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1182 {
1183 return false;
1184 }
1185 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1186 {
1187 }
1188 static inline enum ath_btcoex_scheme
1189 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1190 {
1191 return ATH_BTCOEX_CFG_NONE;
1192 }
1193 #endif
1194
1195
1196 #ifdef CONFIG_ATH9K_WOW
1197 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1198 u8 *user_mask, int pattern_count,
1199 int pattern_len);
1200 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1201 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1202 #else
1203 static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1204 u8 *user_pattern,
1205 u8 *user_mask,
1206 int pattern_count,
1207 int pattern_len)
1208 {
1209 return 0;
1210 }
1211 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1212 {
1213 return 0;
1214 }
1215 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1216 {
1217 }
1218 #endif
1219
1220 #define ATH9K_CLOCK_RATE_CCK 22
1221 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1222 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1223 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1224
1225 #endif