drivers/net/wan/c101.c

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This source file includes following definitions.
sca_get_page
openwin
set_carrier
sca_msci_intr
c101_set_iface
c101_open
c101_close
c101_ioctl
c101_destroy_card
c101_run
c101_init
c101_cleanup
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Moxa C101 synchronous serial card driver for Linux
   4  *
   5  * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
   6  *
   7  * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
   8  *
   9  * Sources of information:
  10  *    Hitachi HD64570 SCA User's Manual
  11  *    Moxa C101 User's Manual
  12  */
  13 
  14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15 
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/capability.h>
  19 #include <linux/slab.h>
  20 #include <linux/types.h>
  21 #include <linux/string.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/hdlc.h>
  26 #include <linux/delay.h>
  27 #include <asm/io.h>
  28 
  29 #include "hd64570.h"
  30 
  31 
  32 static const char* version = "Moxa C101 driver version: 1.15";
  33 static const char* devname = "C101";
  34 
  35 #undef DEBUG_PKT
  36 #define DEBUG_RINGS
  37 
  38 #define C101_PAGE 0x1D00
  39 #define C101_DTR 0x1E00
  40 #define C101_SCA 0x1F00
  41 #define C101_WINDOW_SIZE 0x2000
  42 #define C101_MAPPED_RAM_SIZE 0x4000
  43 
  44 #define RAM_SIZE (256 * 1024)
  45 #define TX_RING_BUFFERS 10
  46 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) /                \
  47                          (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
  48 
  49 #define CLOCK_BASE 9830400      /* 9.8304 MHz */
  50 #define PAGE0_ALWAYS_MAPPED
  51 
  52 static char *hw;                /* pointer to hw=xxx command line string */
  53 
  54 
  55 typedef struct card_s {
  56         struct net_device *dev;
  57         spinlock_t lock;        /* TX lock */
  58         u8 __iomem *win0base;   /* ISA window base address */
  59         u32 phy_winbase;        /* ISA physical base address */
  60         sync_serial_settings settings;
  61         int rxpart;             /* partial frame received, next frame invalid*/
  62         unsigned short encoding;
  63         unsigned short parity;
  64         u16 rx_ring_buffers;    /* number of buffers in a ring */
  65         u16 tx_ring_buffers;
  66         u16 buff_offset;        /* offset of first buffer of first channel */
  67         u16 rxin;               /* rx ring buffer 'in' pointer */
  68         u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
  69         u16 txlast;
  70         u8 rxs, txs, tmc;       /* SCA registers */
  71         u8 irq;                 /* IRQ (3-15) */
  72         u8 page;
  73 
  74         struct card_s *next_card;
  75 }card_t;
  76 
  77 typedef card_t port_t;
  78 
  79 static card_t *first_card;
  80 static card_t **new_card = &first_card;
  81 
  82 
  83 #define sca_in(reg, card)          readb((card)->win0base + C101_SCA + (reg))
  84 #define sca_out(value, reg, card)  writeb(value, (card)->win0base + C101_SCA + (reg))
  85 #define sca_inw(reg, card)         readw((card)->win0base + C101_SCA + (reg))
  86 
  87 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
  88 #define sca_outw(value, reg, card) do { \
  89         writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
  90         writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\
  91 } while(0)
  92 
  93 #define port_to_card(port)         (port)
  94 #define log_node(port)             (0)
  95 #define phy_node(port)             (0)
  96 #define winsize(card)              (C101_WINDOW_SIZE)
  97 #define win0base(card)             ((card)->win0base)
  98 #define winbase(card)              ((card)->win0base + 0x2000)
  99 #define get_port(card, port)       (card)
 100 static void sca_msci_intr(port_t *port);
 101 
 102 
 103 static inline u8 sca_get_page(card_t *card)
 104 {
 105         return card->page;
 106 }
 107 
 108 static inline void openwin(card_t *card, u8 page)
 109 {
 110         card->page = page;
 111         writeb(page, card->win0base + C101_PAGE);
 112 }
 113 
 114 
 115 #include "hd64570.c"
 116 
 117 
 118 static inline void set_carrier(port_t *port)
 119 {
 120         if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))
 121                 netif_carrier_on(port_to_dev(port));
 122         else
 123                 netif_carrier_off(port_to_dev(port));
 124 }
 125 
 126 
 127 static void sca_msci_intr(port_t *port)
 128 {
 129         u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */
 130 
 131         /* Reset MSCI TX underrun and CDCD (ignored) status bit */
 132         sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);
 133 
 134         if (stat & ST1_UDRN) {
 135                 /* TX Underrun error detected */
 136                 port_to_dev(port)->stats.tx_errors++;
 137                 port_to_dev(port)->stats.tx_fifo_errors++;
 138         }
 139 
 140         stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
 141         /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
 142         sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
 143 
 144         if (stat & ST1_CDCD)
 145                 set_carrier(port);
 146 }
 147 
 148 
 149 static void c101_set_iface(port_t *port)
 150 {
 151         u8 rxs = port->rxs & CLK_BRG_MASK;
 152         u8 txs = port->txs & CLK_BRG_MASK;
 153 
 154         switch(port->settings.clock_type) {
 155         case CLOCK_INT:
 156                 rxs |= CLK_BRG_RX; /* TX clock */
 157                 txs |= CLK_RXCLK_TX; /* BRG output */
 158                 break;
 159 
 160         case CLOCK_TXINT:
 161                 rxs |= CLK_LINE_RX; /* RXC input */
 162                 txs |= CLK_BRG_TX; /* BRG output */
 163                 break;
 164 
 165         case CLOCK_TXFROMRX:
 166                 rxs |= CLK_LINE_RX; /* RXC input */
 167                 txs |= CLK_RXCLK_TX; /* RX clock */
 168                 break;
 169 
 170         default:        /* EXTernal clock */
 171                 rxs |= CLK_LINE_RX; /* RXC input */
 172                 txs |= CLK_LINE_TX; /* TXC input */
 173         }
 174 
 175         port->rxs = rxs;
 176         port->txs = txs;
 177         sca_out(rxs, MSCI1_OFFSET + RXS, port);
 178         sca_out(txs, MSCI1_OFFSET + TXS, port);
 179         sca_set_port(port);
 180 }
 181 
 182 
 183 static int c101_open(struct net_device *dev)
 184 {
 185         port_t *port = dev_to_port(dev);
 186         int result;
 187 
 188         result = hdlc_open(dev);
 189         if (result)
 190                 return result;
 191 
 192         writeb(1, port->win0base + C101_DTR);
 193         sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
 194         sca_open(dev);
 195         /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
 196         sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
 197         sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
 198 
 199         set_carrier(port);
 200 
 201         /* enable MSCI1 CDCD interrupt */
 202         sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
 203         sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
 204         sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
 205         c101_set_iface(port);
 206         return 0;
 207 }
 208 
 209 
 210 static int c101_close(struct net_device *dev)
 211 {
 212         port_t *port = dev_to_port(dev);
 213 
 214         sca_close(dev);
 215         writeb(0, port->win0base + C101_DTR);
 216         sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
 217         hdlc_close(dev);
 218         return 0;
 219 }
 220 
 221 
 222 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 223 {
 224         const size_t size = sizeof(sync_serial_settings);
 225         sync_serial_settings new_line;
 226         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 227         port_t *port = dev_to_port(dev);
 228 
 229 #ifdef DEBUG_RINGS
 230         if (cmd == SIOCDEVPRIVATE) {
 231                 sca_dump_rings(dev);
 232                 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
 233                        sca_in(MSCI1_OFFSET + ST0, port),
 234                        sca_in(MSCI1_OFFSET + ST1, port),
 235                        sca_in(MSCI1_OFFSET + ST2, port),
 236                        sca_in(MSCI1_OFFSET + ST3, port));
 237                 return 0;
 238         }
 239 #endif
 240         if (cmd != SIOCWANDEV)
 241                 return hdlc_ioctl(dev, ifr, cmd);
 242 
 243         switch(ifr->ifr_settings.type) {
 244         case IF_GET_IFACE:
 245                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
 246                 if (ifr->ifr_settings.size < size) {
 247                         ifr->ifr_settings.size = size; /* data size wanted */
 248                         return -ENOBUFS;
 249                 }
 250                 if (copy_to_user(line, &port->settings, size))
 251                         return -EFAULT;
 252                 return 0;
 253 
 254         case IF_IFACE_SYNC_SERIAL:
 255                 if(!capable(CAP_NET_ADMIN))
 256                         return -EPERM;
 257 
 258                 if (copy_from_user(&new_line, line, size))
 259                         return -EFAULT;
 260 
 261                 if (new_line.clock_type != CLOCK_EXT &&
 262                     new_line.clock_type != CLOCK_TXFROMRX &&
 263                     new_line.clock_type != CLOCK_INT &&
 264                     new_line.clock_type != CLOCK_TXINT)
 265                         return -EINVAL; /* No such clock setting */
 266 
 267                 if (new_line.loopback != 0 && new_line.loopback != 1)
 268                         return -EINVAL;
 269 
 270                 memcpy(&port->settings, &new_line, size); /* Update settings */
 271                 c101_set_iface(port);
 272                 return 0;
 273 
 274         default:
 275                 return hdlc_ioctl(dev, ifr, cmd);
 276         }
 277 }
 278 
 279 
 280 
 281 static void c101_destroy_card(card_t *card)
 282 {
 283         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 284 
 285         if (card->irq)
 286                 free_irq(card->irq, card);
 287 
 288         if (card->win0base) {
 289                 iounmap(card->win0base);
 290                 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
 291         }
 292 
 293         free_netdev(card->dev);
 294 
 295         kfree(card);
 296 }
 297 
 298 static const struct net_device_ops c101_ops = {
 299         .ndo_open       = c101_open,
 300         .ndo_stop       = c101_close,
 301         .ndo_start_xmit = hdlc_start_xmit,
 302         .ndo_do_ioctl   = c101_ioctl,
 303 };
 304 
 305 static int __init c101_run(unsigned long irq, unsigned long winbase)
 306 {
 307         struct net_device *dev;
 308         hdlc_device *hdlc;
 309         card_t *card;
 310         int result;
 311 
 312         if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
 313                 pr_err("invalid IRQ value\n");
 314                 return -ENODEV;
 315         }
 316 
 317         if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
 318                 pr_err("invalid RAM value\n");
 319                 return -ENODEV;
 320         }
 321 
 322         card = kzalloc(sizeof(card_t), GFP_KERNEL);
 323         if (card == NULL)
 324                 return -ENOBUFS;
 325 
 326         card->dev = alloc_hdlcdev(card);
 327         if (!card->dev) {
 328                 pr_err("unable to allocate memory\n");
 329                 kfree(card);
 330                 return -ENOBUFS;
 331         }
 332 
 333         if (request_irq(irq, sca_intr, 0, devname, card)) {
 334                 pr_err("could not allocate IRQ\n");
 335                 c101_destroy_card(card);
 336                 return -EBUSY;
 337         }
 338         card->irq = irq;
 339 
 340         if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
 341                 pr_err("could not request RAM window\n");
 342                 c101_destroy_card(card);
 343                 return -EBUSY;
 344         }
 345         card->phy_winbase = winbase;
 346         card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
 347         if (!card->win0base) {
 348                 pr_err("could not map I/O address\n");
 349                 c101_destroy_card(card);
 350                 return -EFAULT;
 351         }
 352 
 353         card->tx_ring_buffers = TX_RING_BUFFERS;
 354         card->rx_ring_buffers = RX_RING_BUFFERS;
 355         card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
 356 
 357         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 358         udelay(100);
 359         writeb(0, card->win0base + C101_PAGE);
 360         writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
 361 
 362         sca_init(card, 0);
 363 
 364         dev = port_to_dev(card);
 365         hdlc = dev_to_hdlc(dev);
 366 
 367         spin_lock_init(&card->lock);
 368         dev->irq = irq;
 369         dev->mem_start = winbase;
 370         dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
 371         dev->tx_queue_len = 50;
 372         dev->netdev_ops = &c101_ops;
 373         hdlc->attach = sca_attach;
 374         hdlc->xmit = sca_xmit;
 375         card->settings.clock_type = CLOCK_EXT;
 376 
 377         result = register_hdlc_device(dev);
 378         if (result) {
 379                 pr_warn("unable to register hdlc device\n");
 380                 c101_destroy_card(card);
 381                 return result;
 382         }
 383 
 384         sca_init_port(card); /* Set up C101 memory */
 385         set_carrier(card);
 386 
 387         netdev_info(dev, "Moxa C101 on IRQ%u, using %u TX + %u RX packets rings\n",
 388                     card->irq, card->tx_ring_buffers, card->rx_ring_buffers);
 389 
 390         *new_card = card;
 391         new_card = &card->next_card;
 392         return 0;
 393 }
 394 
 395 
 396 
 397 static int __init c101_init(void)
 398 {
 399         if (hw == NULL) {
 400 #ifdef MODULE
 401                 pr_info("no card initialized\n");
 402 #endif
 403                 return -EINVAL; /* no parameters specified, abort */
 404         }
 405 
 406         pr_info("%s\n", version);
 407 
 408         do {
 409                 unsigned long irq, ram;
 410 
 411                 irq = simple_strtoul(hw, &hw, 0);
 412 
 413                 if (*hw++ != ',')
 414                         break;
 415                 ram = simple_strtoul(hw, &hw, 0);
 416 
 417                 if (*hw == ':' || *hw == '\x0')
 418                         c101_run(irq, ram);
 419 
 420                 if (*hw == '\x0')
 421                         return first_card ? 0 : -EINVAL;
 422         }while(*hw++ == ':');
 423 
 424         pr_err("invalid hardware parameters\n");
 425         return first_card ? 0 : -EINVAL;
 426 }
 427 
 428 
 429 static void __exit c101_cleanup(void)
 430 {
 431         card_t *card = first_card;
 432 
 433         while (card) {
 434                 card_t *ptr = card;
 435                 card = card->next_card;
 436                 unregister_hdlc_device(port_to_dev(ptr));
 437                 c101_destroy_card(ptr);
 438         }
 439 }
 440 
 441 
 442 module_init(c101_init);
 443 module_exit(c101_cleanup);
 444 
 445 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 446 MODULE_DESCRIPTION("Moxa C101 serial port driver");
 447 MODULE_LICENSE("GPL v2");
 448 module_param(hw, charp, 0444);
 449 MODULE_PARM_DESC(hw, "irq,ram:irq,...");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/wan/c101.c

DEFINITIONS
