This source file includes following definitions.
- mlxsw_pci_queue_tasklet_schedule
- __mlxsw_pci_queue_elem_get
- mlxsw_pci_queue_elem_info_get
- mlxsw_pci_queue_elem_info_producer_get
- mlxsw_pci_queue_elem_info_consumer_get
- mlxsw_pci_queue_elem_get
- mlxsw_pci_elem_hw_owned
- mlxsw_pci_queue_type_group_get
- __mlxsw_pci_queue_count
- mlxsw_pci_sdq_count
- mlxsw_pci_cq_count
- __mlxsw_pci_queue_get
- mlxsw_pci_sdq_get
- mlxsw_pci_rdq_get
- mlxsw_pci_cq_get
- mlxsw_pci_eq_get
- __mlxsw_pci_queue_doorbell_set
- __mlxsw_pci_queue_doorbell_arm_set
- mlxsw_pci_queue_doorbell_producer_ring
- mlxsw_pci_queue_doorbell_consumer_ring
- mlxsw_pci_queue_doorbell_arm_consumer_ring
- __mlxsw_pci_queue_page_get
- mlxsw_pci_sdq_init
- mlxsw_pci_sdq_fini
- mlxsw_pci_wqe_frag_map
- mlxsw_pci_wqe_frag_unmap
- mlxsw_pci_rdq_skb_alloc
- mlxsw_pci_rdq_skb_free
- mlxsw_pci_rdq_init
- mlxsw_pci_rdq_fini
- mlxsw_pci_cq_pre_init
- mlxsw_pci_cq_init
- mlxsw_pci_cq_fini
- mlxsw_pci_cqe_sdq_handle
- mlxsw_pci_cqe_rdq_handle
- mlxsw_pci_cq_sw_cqe_get
- mlxsw_pci_cq_tasklet
- mlxsw_pci_cq_elem_count
- mlxsw_pci_cq_elem_size
- mlxsw_pci_eq_init
- mlxsw_pci_eq_fini
- mlxsw_pci_eq_cmd_event
- mlxsw_pci_eq_sw_eqe_get
- mlxsw_pci_eq_tasklet
- mlxsw_pci_queue_init
- mlxsw_pci_queue_fini
- mlxsw_pci_queue_group_init
- mlxsw_pci_queue_group_fini
- mlxsw_pci_aqs_init
- mlxsw_pci_aqs_fini
- mlxsw_pci_config_profile_swid_config
- mlxsw_pci_profile_get_kvd_sizes
- mlxsw_pci_config_profile
- mlxsw_pci_boardinfo
- mlxsw_pci_fw_area_init
- mlxsw_pci_fw_area_fini
- mlxsw_pci_eq_irq_handler
- mlxsw_pci_mbox_alloc
- mlxsw_pci_mbox_free
- mlxsw_pci_sys_ready_wait
- mlxsw_pci_sw_reset
- mlxsw_pci_alloc_irq_vectors
- mlxsw_pci_free_irq_vectors
- mlxsw_pci_init
- mlxsw_pci_fini
- mlxsw_pci_sdq_pick
- mlxsw_pci_skb_transmit_busy
- mlxsw_pci_skb_transmit
- mlxsw_pci_cmd_exec
- mlxsw_pci_read_frc_h
- mlxsw_pci_read_frc_l
- mlxsw_pci_probe
- mlxsw_pci_remove
- mlxsw_pci_driver_register
- mlxsw_pci_driver_unregister
- mlxsw_pci_module_init
- mlxsw_pci_module_exit
1
2
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/export.h>
7 #include <linux/err.h>
8 #include <linux/device.h>
9 #include <linux/pci.h>
10 #include <linux/interrupt.h>
11 #include <linux/wait.h>
12 #include <linux/types.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/log2.h>
16 #include <linux/string.h>
17
18 #include "pci_hw.h"
19 #include "pci.h"
20 #include "core.h"
21 #include "cmd.h"
22 #include "port.h"
23 #include "resources.h"
24
25 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \
26 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
27 #define mlxsw_pci_read32(mlxsw_pci, reg) \
28 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg))
29
30 enum mlxsw_pci_queue_type {
31 MLXSW_PCI_QUEUE_TYPE_SDQ,
32 MLXSW_PCI_QUEUE_TYPE_RDQ,
33 MLXSW_PCI_QUEUE_TYPE_CQ,
34 MLXSW_PCI_QUEUE_TYPE_EQ,
35 };
36
37 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4
38
39 static const u16 mlxsw_pci_doorbell_type_offset[] = {
40 MLXSW_PCI_DOORBELL_SDQ_OFFSET,
41 MLXSW_PCI_DOORBELL_RDQ_OFFSET,
42 MLXSW_PCI_DOORBELL_CQ_OFFSET,
43 MLXSW_PCI_DOORBELL_EQ_OFFSET,
44 };
45
46 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = {
47 0,
48 0,
49 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET,
50 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET,
51 };
52
53 struct mlxsw_pci_mem_item {
54 char *buf;
55 dma_addr_t mapaddr;
56 size_t size;
57 };
58
59 struct mlxsw_pci_queue_elem_info {
60 char *elem;
61 union {
62 struct {
63 struct sk_buff *skb;
64 } sdq;
65 struct {
66 struct sk_buff *skb;
67 } rdq;
68 } u;
69 };
70
71 struct mlxsw_pci_queue {
72 spinlock_t lock;
73 struct mlxsw_pci_mem_item mem_item;
74 struct mlxsw_pci_queue_elem_info *elem_info;
75 u16 producer_counter;
76 u16 consumer_counter;
77 u16 count;
78 u8 num;
79 u8 elem_size;
80 enum mlxsw_pci_queue_type type;
81 struct tasklet_struct tasklet;
82 struct mlxsw_pci *pci;
83 union {
84 struct {
85 u32 comp_sdq_count;
86 u32 comp_rdq_count;
87 enum mlxsw_pci_cqe_v v;
88 } cq;
89 struct {
90 u32 ev_cmd_count;
91 u32 ev_comp_count;
92 u32 ev_other_count;
93 } eq;
94 } u;
95 };
96
97 struct mlxsw_pci_queue_type_group {
98 struct mlxsw_pci_queue *q;
99 u8 count;
100 };
101
102 struct mlxsw_pci {
103 struct pci_dev *pdev;
104 u8 __iomem *hw_addr;
105 u64 free_running_clock_offset;
106 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
107 u32 doorbell_offset;
108 struct mlxsw_core *core;
109 struct {
110 struct mlxsw_pci_mem_item *items;
111 unsigned int count;
112 } fw_area;
113 struct {
114 struct mlxsw_pci_mem_item out_mbox;
115 struct mlxsw_pci_mem_item in_mbox;
116 struct mutex lock;
117 bool nopoll;
118 wait_queue_head_t wait;
119 bool wait_done;
120 struct {
121 u8 status;
122 u64 out_param;
123 } comp;
124 } cmd;
125 struct mlxsw_bus_info bus_info;
126 const struct pci_device_id *id;
127 enum mlxsw_pci_cqe_v max_cqe_ver;
128 u8 num_sdq_cqs;
129 };
130
131 static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q)
132 {
133 tasklet_schedule(&q->tasklet);
134 }
135
136 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q,
137 size_t elem_size, int elem_index)
138 {
139 return q->mem_item.buf + (elem_size * elem_index);
140 }
141
142 static struct mlxsw_pci_queue_elem_info *
143 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index)
144 {
145 return &q->elem_info[elem_index];
146 }
147
148 static struct mlxsw_pci_queue_elem_info *
149 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q)
150 {
151 int index = q->producer_counter & (q->count - 1);
152
153 if ((u16) (q->producer_counter - q->consumer_counter) == q->count)
154 return NULL;
155 return mlxsw_pci_queue_elem_info_get(q, index);
156 }
157
158 static struct mlxsw_pci_queue_elem_info *
159 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q)
160 {
161 int index = q->consumer_counter & (q->count - 1);
162
163 return mlxsw_pci_queue_elem_info_get(q, index);
164 }
165
166 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index)
167 {
168 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem;
169 }
170
171 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit)
172 {
173 return owner_bit != !!(q->consumer_counter & q->count);
174 }
175
176 static struct mlxsw_pci_queue_type_group *
177 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci,
178 enum mlxsw_pci_queue_type q_type)
179 {
180 return &mlxsw_pci->queues[q_type];
181 }
182
183 static u8 __mlxsw_pci_queue_count(struct mlxsw_pci *mlxsw_pci,
184 enum mlxsw_pci_queue_type q_type)
185 {
186 struct mlxsw_pci_queue_type_group *queue_group;
187
188 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_type);
189 return queue_group->count;
190 }
191
192 static u8 mlxsw_pci_sdq_count(struct mlxsw_pci *mlxsw_pci)
193 {
194 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_SDQ);
195 }
196
197 static u8 mlxsw_pci_cq_count(struct mlxsw_pci *mlxsw_pci)
198 {
199 return __mlxsw_pci_queue_count(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ);
200 }
201
202 static struct mlxsw_pci_queue *
203 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci,
204 enum mlxsw_pci_queue_type q_type, u8 q_num)
205 {
206 return &mlxsw_pci->queues[q_type].q[q_num];
207 }
208
209 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci,
210 u8 q_num)
211 {
212 return __mlxsw_pci_queue_get(mlxsw_pci,
213 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num);
214 }
215
216 static struct mlxsw_pci_queue *mlxsw_pci_rdq_get(struct mlxsw_pci *mlxsw_pci,
217 u8 q_num)
218 {
219 return __mlxsw_pci_queue_get(mlxsw_pci,
220 MLXSW_PCI_QUEUE_TYPE_RDQ, q_num);
221 }
222
223 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci,
224 u8 q_num)
225 {
226 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num);
227 }
228
229 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci,
230 u8 q_num)
231 {
232 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, q_num);
233 }
234
235 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci,
236 struct mlxsw_pci_queue *q,
237 u16 val)
238 {
239 mlxsw_pci_write32(mlxsw_pci,
240 DOORBELL(mlxsw_pci->doorbell_offset,
241 mlxsw_pci_doorbell_type_offset[q->type],
242 q->num), val);
243 }
244
245 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci,
246 struct mlxsw_pci_queue *q,
247 u16 val)
248 {
249 mlxsw_pci_write32(mlxsw_pci,
250 DOORBELL(mlxsw_pci->doorbell_offset,
251 mlxsw_pci_doorbell_arm_type_offset[q->type],
252 q->num), val);
253 }
254
255 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci,
256 struct mlxsw_pci_queue *q)
257 {
258 wmb();
259 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter);
260 }
261
262 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci,
263 struct mlxsw_pci_queue *q)
264 {
265 wmb();
266 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q,
267 q->consumer_counter + q->count);
268 }
269
270 static void
271 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci,
272 struct mlxsw_pci_queue *q)
273 {
274 wmb();
275 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter);
276 }
277
278 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q,
279 int page_index)
280 {
281 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index;
282 }
283
284 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
285 struct mlxsw_pci_queue *q)
286 {
287 int i;
288 int err;
289
290 q->producer_counter = 0;
291 q->consumer_counter = 0;
292
293
294 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);
295 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, 3);
296 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3);
297 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
298 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
299
300 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
301 }
302
303 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);
304 if (err)
305 return err;
306 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
307 return 0;
308 }
309
310 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci,
311 struct mlxsw_pci_queue *q)
312 {
313 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num);
314 }
315
316 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe,
317 int index, char *frag_data, size_t frag_len,
318 int direction)
319 {
320 struct pci_dev *pdev = mlxsw_pci->pdev;
321 dma_addr_t mapaddr;
322
323 mapaddr = pci_map_single(pdev, frag_data, frag_len, direction);
324 if (unlikely(pci_dma_mapping_error(pdev, mapaddr))) {
325 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n");
326 return -EIO;
327 }
328 mlxsw_pci_wqe_address_set(wqe, index, mapaddr);
329 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len);
330 return 0;
331 }
332
333 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe,
334 int index, int direction)
335 {
336 struct pci_dev *pdev = mlxsw_pci->pdev;
337 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index);
338 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index);
339
340 if (!frag_len)
341 return;
342 pci_unmap_single(pdev, mapaddr, frag_len, direction);
343 }
344
345 static int mlxsw_pci_rdq_skb_alloc(struct mlxsw_pci *mlxsw_pci,
346 struct mlxsw_pci_queue_elem_info *elem_info)
347 {
348 size_t buf_len = MLXSW_PORT_MAX_MTU;
349 char *wqe = elem_info->elem;
350 struct sk_buff *skb;
351 int err;
352
353 elem_info->u.rdq.skb = NULL;
354 skb = netdev_alloc_skb_ip_align(NULL, buf_len);
355 if (!skb)
356 return -ENOMEM;
357
358
359
360 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
361 buf_len, DMA_FROM_DEVICE);
362 if (err)
363 goto err_frag_map;
364
365 elem_info->u.rdq.skb = skb;
366 return 0;
367
368 err_frag_map:
369 dev_kfree_skb_any(skb);
370 return err;
371 }
372
373 static void mlxsw_pci_rdq_skb_free(struct mlxsw_pci *mlxsw_pci,
374 struct mlxsw_pci_queue_elem_info *elem_info)
375 {
376 struct sk_buff *skb;
377 char *wqe;
378
379 skb = elem_info->u.rdq.skb;
380 wqe = elem_info->elem;
381
382 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
383 dev_kfree_skb_any(skb);
384 }
385
386 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
387 struct mlxsw_pci_queue *q)
388 {
389 struct mlxsw_pci_queue_elem_info *elem_info;
390 u8 sdq_count = mlxsw_pci_sdq_count(mlxsw_pci);
391 int i;
392 int err;
393
394 q->producer_counter = 0;
395 q->consumer_counter = 0;
396
397
398
399
400 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);
401 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3);
402 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
403 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
404
405 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);
406 }
407
408 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);
409 if (err)
410 return err;
411
412 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
413
414 for (i = 0; i < q->count; i++) {
415 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
416 BUG_ON(!elem_info);
417 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
418 if (err)
419 goto rollback;
420
421 q->producer_counter++;
422 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
423 }
424
425 return 0;
426
427 rollback:
428 for (i--; i >= 0; i--) {
429 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
430 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
431 }
432 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
433
434 return err;
435 }
436
437 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci,
438 struct mlxsw_pci_queue *q)
439 {
440 struct mlxsw_pci_queue_elem_info *elem_info;
441 int i;
442
443 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num);
444 for (i = 0; i < q->count; i++) {
445 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
446 mlxsw_pci_rdq_skb_free(mlxsw_pci, elem_info);
447 }
448 }
449
450 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci,
451 struct mlxsw_pci_queue *q)
452 {
453 q->u.cq.v = mlxsw_pci->max_cqe_ver;
454
455
456 if (q->u.cq.v == MLXSW_PCI_CQE_V2 &&
457 q->num < mlxsw_pci->num_sdq_cqs)
458 q->u.cq.v = MLXSW_PCI_CQE_V1;
459 }
460
461 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
462 struct mlxsw_pci_queue *q)
463 {
464 int i;
465 int err;
466
467 q->consumer_counter = 0;
468
469 for (i = 0; i < q->count; i++) {
470 char *elem = mlxsw_pci_queue_elem_get(q, i);
471
472 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1);
473 }
474
475 if (q->u.cq.v == MLXSW_PCI_CQE_V1)
476 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
477 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1);
478 else if (q->u.cq.v == MLXSW_PCI_CQE_V2)
479 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,
480 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2);
481
482 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);
483 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);
484 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));
485 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
486 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
487
488 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);
489 }
490 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);
491 if (err)
492 return err;
493 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
494 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
495 return 0;
496 }
497
498 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci,
499 struct mlxsw_pci_queue *q)
500 {
501 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num);
502 }
503
504 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci,
505 struct mlxsw_pci_queue *q,
506 u16 consumer_counter_limit,
507 char *cqe)
508 {
509 struct pci_dev *pdev = mlxsw_pci->pdev;
510 struct mlxsw_pci_queue_elem_info *elem_info;
511 struct mlxsw_tx_info tx_info;
512 char *wqe;
513 struct sk_buff *skb;
514 int i;
515
516 spin_lock(&q->lock);
517 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
518 tx_info = mlxsw_skb_cb(elem_info->u.sdq.skb)->tx_info;
519 skb = elem_info->u.sdq.skb;
520 wqe = elem_info->elem;
521 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
522 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
523
524 if (unlikely(!tx_info.is_emad &&
525 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
526 mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb,
527 tx_info.local_port);
528 skb = NULL;
529 }
530
531 if (skb)
532 dev_kfree_skb_any(skb);
533 elem_info->u.sdq.skb = NULL;
534
535 if (q->consumer_counter++ != consumer_counter_limit)
536 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n");
537 spin_unlock(&q->lock);
538 }
539
540 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci,
541 struct mlxsw_pci_queue *q,
542 u16 consumer_counter_limit,
543 enum mlxsw_pci_cqe_v cqe_v, char *cqe)
544 {
545 struct pci_dev *pdev = mlxsw_pci->pdev;
546 struct mlxsw_pci_queue_elem_info *elem_info;
547 char *wqe;
548 struct sk_buff *skb;
549 struct mlxsw_rx_info rx_info;
550 u16 byte_count;
551 int err;
552
553 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
554 skb = elem_info->u.sdq.skb;
555 if (!skb)
556 return;
557 wqe = elem_info->elem;
558 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, 0, DMA_FROM_DEVICE);
559
560 if (q->consumer_counter++ != consumer_counter_limit)
561 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n");
562
563 if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) {
564 rx_info.is_lag = true;
565 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe);
566 rx_info.lag_port_index =
567 mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe);
568 } else {
569 rx_info.is_lag = false;
570 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe);
571 }
572
573 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe);
574
575 byte_count = mlxsw_pci_cqe_byte_count_get(cqe);
576 if (mlxsw_pci_cqe_crc_get(cqe_v, cqe))
577 byte_count -= ETH_FCS_LEN;
578 skb_put(skb, byte_count);
579 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info);
580
581 memset(wqe, 0, q->elem_size);
582 err = mlxsw_pci_rdq_skb_alloc(mlxsw_pci, elem_info);
583 if (err)
584 dev_dbg_ratelimited(&pdev->dev, "Failed to alloc skb for RDQ\n");
585
586 q->producer_counter++;
587 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
588 return;
589 }
590
591 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q)
592 {
593 struct mlxsw_pci_queue_elem_info *elem_info;
594 char *elem;
595 bool owner_bit;
596
597 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
598 elem = elem_info->elem;
599 owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem);
600 if (mlxsw_pci_elem_hw_owned(q, owner_bit))
601 return NULL;
602 q->consumer_counter++;
603 rmb();
604 return elem;
605 }
606
607 static void mlxsw_pci_cq_tasklet(unsigned long data)
608 {
609 struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
610 struct mlxsw_pci *mlxsw_pci = q->pci;
611 char *cqe;
612 int items = 0;
613 int credits = q->count >> 1;
614
615 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) {
616 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe);
617 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe);
618 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe);
619 char ncqe[MLXSW_PCI_CQE_SIZE_MAX];
620
621 memcpy(ncqe, cqe, q->elem_size);
622 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
623
624 if (sendq) {
625 struct mlxsw_pci_queue *sdq;
626
627 sdq = mlxsw_pci_sdq_get(mlxsw_pci, dqn);
628 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq,
629 wqe_counter, ncqe);
630 q->u.cq.comp_sdq_count++;
631 } else {
632 struct mlxsw_pci_queue *rdq;
633
634 rdq = mlxsw_pci_rdq_get(mlxsw_pci, dqn);
635 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq,
636 wqe_counter, q->u.cq.v, ncqe);
637 q->u.cq.comp_rdq_count++;
638 }
639 if (++items == credits)
640 break;
641 }
642 if (items)
643 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
644 }
645
646 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q)
647 {
648 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT :
649 MLXSW_PCI_CQE01_COUNT;
650 }
651
652 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q)
653 {
654 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE :
655 MLXSW_PCI_CQE01_SIZE;
656 }
657
658 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
659 struct mlxsw_pci_queue *q)
660 {
661 int i;
662 int err;
663
664 q->consumer_counter = 0;
665
666 for (i = 0; i < q->count; i++) {
667 char *elem = mlxsw_pci_queue_elem_get(q, i);
668
669 mlxsw_pci_eqe_owner_set(elem, 1);
670 }
671
672 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1);
673 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1);
674 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));
675 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) {
676 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i);
677
678 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);
679 }
680 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);
681 if (err)
682 return err;
683 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
684 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
685 return 0;
686 }
687
688 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci,
689 struct mlxsw_pci_queue *q)
690 {
691 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num);
692 }
693
694 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe)
695 {
696 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe);
697 mlxsw_pci->cmd.comp.out_param =
698 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 |
699 mlxsw_pci_eqe_cmd_out_param_l_get(eqe);
700 mlxsw_pci->cmd.wait_done = true;
701 wake_up(&mlxsw_pci->cmd.wait);
702 }
703
704 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q)
705 {
706 struct mlxsw_pci_queue_elem_info *elem_info;
707 char *elem;
708 bool owner_bit;
709
710 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q);
711 elem = elem_info->elem;
712 owner_bit = mlxsw_pci_eqe_owner_get(elem);
713 if (mlxsw_pci_elem_hw_owned(q, owner_bit))
714 return NULL;
715 q->consumer_counter++;
716 rmb();
717 return elem;
718 }
719
720 static void mlxsw_pci_eq_tasklet(unsigned long data)
721 {
722 struct mlxsw_pci_queue *q = (struct mlxsw_pci_queue *) data;
723 struct mlxsw_pci *mlxsw_pci = q->pci;
724 u8 cq_count = mlxsw_pci_cq_count(mlxsw_pci);
725 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)];
726 char *eqe;
727 u8 cqn;
728 bool cq_handle = false;
729 int items = 0;
730 int credits = q->count >> 1;
731
732 memset(&active_cqns, 0, sizeof(active_cqns));
733
734 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) {
735
736
737
738
739
740 switch (q->num) {
741 case MLXSW_PCI_EQ_ASYNC_NUM:
742 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe);
743 q->u.eq.ev_cmd_count++;
744 break;
745 case MLXSW_PCI_EQ_COMP_NUM:
746 cqn = mlxsw_pci_eqe_cqn_get(eqe);
747 set_bit(cqn, active_cqns);
748 cq_handle = true;
749 q->u.eq.ev_comp_count++;
750 break;
751 default:
752 q->u.eq.ev_other_count++;
753 }
754 if (++items == credits)
755 break;
756 }
757 if (items) {
758 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q);
759 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q);
760 }
761
762 if (!cq_handle)
763 return;
764 for_each_set_bit(cqn, active_cqns, cq_count) {
765 q = mlxsw_pci_cq_get(mlxsw_pci, cqn);
766 mlxsw_pci_queue_tasklet_schedule(q);
767 }
768 }
769
770 struct mlxsw_pci_queue_ops {
771 const char *name;
772 enum mlxsw_pci_queue_type type;
773 void (*pre_init)(struct mlxsw_pci *mlxsw_pci,
774 struct mlxsw_pci_queue *q);
775 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
776 struct mlxsw_pci_queue *q);
777 void (*fini)(struct mlxsw_pci *mlxsw_pci,
778 struct mlxsw_pci_queue *q);
779 void (*tasklet)(unsigned long data);
780 u16 (*elem_count_f)(const struct mlxsw_pci_queue *q);
781 u8 (*elem_size_f)(const struct mlxsw_pci_queue *q);
782 u16 elem_count;
783 u8 elem_size;
784 };
785
786 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = {
787 .type = MLXSW_PCI_QUEUE_TYPE_SDQ,
788 .init = mlxsw_pci_sdq_init,
789 .fini = mlxsw_pci_sdq_fini,
790 .elem_count = MLXSW_PCI_WQE_COUNT,
791 .elem_size = MLXSW_PCI_WQE_SIZE,
792 };
793
794 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = {
795 .type = MLXSW_PCI_QUEUE_TYPE_RDQ,
796 .init = mlxsw_pci_rdq_init,
797 .fini = mlxsw_pci_rdq_fini,
798 .elem_count = MLXSW_PCI_WQE_COUNT,
799 .elem_size = MLXSW_PCI_WQE_SIZE
800 };
801
802 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = {
803 .type = MLXSW_PCI_QUEUE_TYPE_CQ,
804 .pre_init = mlxsw_pci_cq_pre_init,
805 .init = mlxsw_pci_cq_init,
806 .fini = mlxsw_pci_cq_fini,
807 .tasklet = mlxsw_pci_cq_tasklet,
808 .elem_count_f = mlxsw_pci_cq_elem_count,
809 .elem_size_f = mlxsw_pci_cq_elem_size
810 };
811
812 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = {
813 .type = MLXSW_PCI_QUEUE_TYPE_EQ,
814 .init = mlxsw_pci_eq_init,
815 .fini = mlxsw_pci_eq_fini,
816 .tasklet = mlxsw_pci_eq_tasklet,
817 .elem_count = MLXSW_PCI_EQE_COUNT,
818 .elem_size = MLXSW_PCI_EQE_SIZE
819 };
820
821 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
822 const struct mlxsw_pci_queue_ops *q_ops,
823 struct mlxsw_pci_queue *q, u8 q_num)
824 {
825 struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
826 int i;
827 int err;
828
829 q->num = q_num;
830 if (q_ops->pre_init)
831 q_ops->pre_init(mlxsw_pci, q);
832
833 spin_lock_init(&q->lock);
834 q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) :
835 q_ops->elem_count;
836 q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) :
837 q_ops->elem_size;
838 q->type = q_ops->type;
839 q->pci = mlxsw_pci;
840
841 if (q_ops->tasklet)
842 tasklet_init(&q->tasklet, q_ops->tasklet, (unsigned long) q);
843
844 mem_item->size = MLXSW_PCI_AQ_SIZE;
845 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
846 mem_item->size,
847 &mem_item->mapaddr);
848 if (!mem_item->buf)
849 return -ENOMEM;
850
851 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL);
852 if (!q->elem_info) {
853 err = -ENOMEM;
854 goto err_elem_info_alloc;
855 }
856
857
858
859
860 for (i = 0; i < q->count; i++) {
861 struct mlxsw_pci_queue_elem_info *elem_info;
862
863 elem_info = mlxsw_pci_queue_elem_info_get(q, i);
864 elem_info->elem =
865 __mlxsw_pci_queue_elem_get(q, q->elem_size, i);
866 }
867
868 mlxsw_cmd_mbox_zero(mbox);
869 err = q_ops->init(mlxsw_pci, mbox, q);
870 if (err)
871 goto err_q_ops_init;
872 return 0;
873
874 err_q_ops_init:
875 kfree(q->elem_info);
876 err_elem_info_alloc:
877 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
878 mem_item->buf, mem_item->mapaddr);
879 return err;
880 }
881
882 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci,
883 const struct mlxsw_pci_queue_ops *q_ops,
884 struct mlxsw_pci_queue *q)
885 {
886 struct mlxsw_pci_mem_item *mem_item = &q->mem_item;
887
888 q_ops->fini(mlxsw_pci, q);
889 kfree(q->elem_info);
890 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
891 mem_item->buf, mem_item->mapaddr);
892 }
893
894 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
895 const struct mlxsw_pci_queue_ops *q_ops,
896 u8 num_qs)
897 {
898 struct mlxsw_pci_queue_type_group *queue_group;
899 int i;
900 int err;
901
902 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
903 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL);
904 if (!queue_group->q)
905 return -ENOMEM;
906
907 for (i = 0; i < num_qs; i++) {
908 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,
909 &queue_group->q[i], i);
910 if (err)
911 goto err_queue_init;
912 }
913 queue_group->count = num_qs;
914
915 return 0;
916
917 err_queue_init:
918 for (i--; i >= 0; i--)
919 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
920 kfree(queue_group->q);
921 return err;
922 }
923
924 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci,
925 const struct mlxsw_pci_queue_ops *q_ops)
926 {
927 struct mlxsw_pci_queue_type_group *queue_group;
928 int i;
929
930 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type);
931 for (i = 0; i < queue_group->count; i++)
932 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]);
933 kfree(queue_group->q);
934 }
935
936 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)
937 {
938 struct pci_dev *pdev = mlxsw_pci->pdev;
939 u8 num_sdqs;
940 u8 sdq_log2sz;
941 u8 num_rdqs;
942 u8 rdq_log2sz;
943 u8 num_cqs;
944 u8 cq_log2sz;
945 u8 cqv2_log2sz;
946 u8 num_eqs;
947 u8 eq_log2sz;
948 int err;
949
950 mlxsw_cmd_mbox_zero(mbox);
951 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);
952 if (err)
953 return err;
954
955 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);
956 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);
957 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);
958 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);
959 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);
960 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);
961 cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);
962 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);
963 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);
964
965 if (num_sdqs + num_rdqs > num_cqs ||
966 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_COUNT) {
967 dev_err(&pdev->dev, "Unsupported number of queues\n");
968 return -EINVAL;
969 }
970
971 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
972 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) ||
973 (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) ||
974 (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 &&
975 (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) ||
976 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) {
977 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n");
978 return -EINVAL;
979 }
980
981 mlxsw_pci->num_sdq_cqs = num_sdqs;
982
983 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,
984 num_eqs);
985 if (err) {
986 dev_err(&pdev->dev, "Failed to initialize event queues\n");
987 return err;
988 }
989
990 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,
991 num_cqs);
992 if (err) {
993 dev_err(&pdev->dev, "Failed to initialize completion queues\n");
994 goto err_cqs_init;
995 }
996
997 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,
998 num_sdqs);
999 if (err) {
1000 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n");
1001 goto err_sdqs_init;
1002 }
1003
1004 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,
1005 num_rdqs);
1006 if (err) {
1007 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n");
1008 goto err_rdqs_init;
1009 }
1010
1011
1012 mlxsw_pci->cmd.nopoll = true;
1013 return 0;
1014
1015 err_rdqs_init:
1016 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1017 err_sdqs_init:
1018 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1019 err_cqs_init:
1020 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1021 return err;
1022 }
1023
1024 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci)
1025 {
1026 mlxsw_pci->cmd.nopoll = false;
1027 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops);
1028 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops);
1029 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops);
1030 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops);
1031 }
1032
1033 static void
1034 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
1035 char *mbox, int index,
1036 const struct mlxsw_swid_config *swid)
1037 {
1038 u8 mask = 0;
1039
1040 if (swid->used_type) {
1041 mlxsw_cmd_mbox_config_profile_swid_config_type_set(
1042 mbox, index, swid->type);
1043 mask |= 1;
1044 }
1045 if (swid->used_properties) {
1046 mlxsw_cmd_mbox_config_profile_swid_config_properties_set(
1047 mbox, index, swid->properties);
1048 mask |= 2;
1049 }
1050 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);
1051 }
1052
1053 static int
1054 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci,
1055 const struct mlxsw_config_profile *profile,
1056 struct mlxsw_res *res)
1057 {
1058 u64 single_size, double_size, linear_size;
1059 int err;
1060
1061 err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile,
1062 &single_size, &double_size,
1063 &linear_size);
1064 if (err)
1065 return err;
1066
1067 MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size);
1068 MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size);
1069 MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size);
1070
1071 return 0;
1072 }
1073
1074 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,
1075 const struct mlxsw_config_profile *profile,
1076 struct mlxsw_res *res)
1077 {
1078 int i;
1079 int err;
1080
1081 mlxsw_cmd_mbox_zero(mbox);
1082
1083 if (profile->used_max_vepa_channels) {
1084 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set(
1085 mbox, 1);
1086 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set(
1087 mbox, profile->max_vepa_channels);
1088 }
1089 if (profile->used_max_mid) {
1090 mlxsw_cmd_mbox_config_profile_set_max_mid_set(
1091 mbox, 1);
1092 mlxsw_cmd_mbox_config_profile_max_mid_set(
1093 mbox, profile->max_mid);
1094 }
1095 if (profile->used_max_pgt) {
1096 mlxsw_cmd_mbox_config_profile_set_max_pgt_set(
1097 mbox, 1);
1098 mlxsw_cmd_mbox_config_profile_max_pgt_set(
1099 mbox, profile->max_pgt);
1100 }
1101 if (profile->used_max_system_port) {
1102 mlxsw_cmd_mbox_config_profile_set_max_system_port_set(
1103 mbox, 1);
1104 mlxsw_cmd_mbox_config_profile_max_system_port_set(
1105 mbox, profile->max_system_port);
1106 }
1107 if (profile->used_max_vlan_groups) {
1108 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set(
1109 mbox, 1);
1110 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set(
1111 mbox, profile->max_vlan_groups);
1112 }
1113 if (profile->used_max_regions) {
1114 mlxsw_cmd_mbox_config_profile_set_max_regions_set(
1115 mbox, 1);
1116 mlxsw_cmd_mbox_config_profile_max_regions_set(
1117 mbox, profile->max_regions);
1118 }
1119 if (profile->used_flood_tables) {
1120 mlxsw_cmd_mbox_config_profile_set_flood_tables_set(
1121 mbox, 1);
1122 mlxsw_cmd_mbox_config_profile_max_flood_tables_set(
1123 mbox, profile->max_flood_tables);
1124 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set(
1125 mbox, profile->max_vid_flood_tables);
1126 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set(
1127 mbox, profile->max_fid_offset_flood_tables);
1128 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set(
1129 mbox, profile->fid_offset_flood_table_size);
1130 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set(
1131 mbox, profile->max_fid_flood_tables);
1132 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set(
1133 mbox, profile->fid_flood_table_size);
1134 }
1135 if (profile->used_flood_mode) {
1136 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(
1137 mbox, 1);
1138 mlxsw_cmd_mbox_config_profile_flood_mode_set(
1139 mbox, profile->flood_mode);
1140 }
1141 if (profile->used_max_ib_mc) {
1142 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set(
1143 mbox, 1);
1144 mlxsw_cmd_mbox_config_profile_max_ib_mc_set(
1145 mbox, profile->max_ib_mc);
1146 }
1147 if (profile->used_max_pkey) {
1148 mlxsw_cmd_mbox_config_profile_set_max_pkey_set(
1149 mbox, 1);
1150 mlxsw_cmd_mbox_config_profile_max_pkey_set(
1151 mbox, profile->max_pkey);
1152 }
1153 if (profile->used_ar_sec) {
1154 mlxsw_cmd_mbox_config_profile_set_ar_sec_set(
1155 mbox, 1);
1156 mlxsw_cmd_mbox_config_profile_ar_sec_set(
1157 mbox, profile->ar_sec);
1158 }
1159 if (profile->used_adaptive_routing_group_cap) {
1160 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set(
1161 mbox, 1);
1162 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set(
1163 mbox, profile->adaptive_routing_group_cap);
1164 }
1165 if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) {
1166 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res);
1167 if (err)
1168 return err;
1169
1170 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);
1171 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,
1172 MLXSW_RES_GET(res, KVD_LINEAR_SIZE));
1173 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,
1174 1);
1175 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,
1176 MLXSW_RES_GET(res, KVD_SINGLE_SIZE));
1177 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set(
1178 mbox, 1);
1179 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,
1180 MLXSW_RES_GET(res, KVD_DOUBLE_SIZE));
1181 }
1182
1183 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++)
1184 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,
1185 &profile->swid_config[i]);
1186
1187 if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) {
1188 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);
1189 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);
1190 }
1191
1192 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);
1193 }
1194
1195 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)
1196 {
1197 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info;
1198 int err;
1199
1200 mlxsw_cmd_mbox_zero(mbox);
1201 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);
1202 if (err)
1203 return err;
1204 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);
1205 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);
1206 return 0;
1207 }
1208
1209 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,
1210 u16 num_pages)
1211 {
1212 struct mlxsw_pci_mem_item *mem_item;
1213 int nent = 0;
1214 int i;
1215 int err;
1216
1217 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item),
1218 GFP_KERNEL);
1219 if (!mlxsw_pci->fw_area.items)
1220 return -ENOMEM;
1221 mlxsw_pci->fw_area.count = num_pages;
1222
1223 mlxsw_cmd_mbox_zero(mbox);
1224 for (i = 0; i < num_pages; i++) {
1225 mem_item = &mlxsw_pci->fw_area.items[i];
1226
1227 mem_item->size = MLXSW_PCI_PAGE_SIZE;
1228 mem_item->buf = pci_alloc_consistent(mlxsw_pci->pdev,
1229 mem_item->size,
1230 &mem_item->mapaddr);
1231 if (!mem_item->buf) {
1232 err = -ENOMEM;
1233 goto err_alloc;
1234 }
1235 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);
1236 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0);
1237 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) {
1238 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1239 if (err)
1240 goto err_cmd_map_fa;
1241 nent = 0;
1242 mlxsw_cmd_mbox_zero(mbox);
1243 }
1244 }
1245
1246 if (nent) {
1247 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);
1248 if (err)
1249 goto err_cmd_map_fa;
1250 }
1251
1252 return 0;
1253
1254 err_cmd_map_fa:
1255 err_alloc:
1256 for (i--; i >= 0; i--) {
1257 mem_item = &mlxsw_pci->fw_area.items[i];
1258
1259 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1260 mem_item->buf, mem_item->mapaddr);
1261 }
1262 kfree(mlxsw_pci->fw_area.items);
1263 return err;
1264 }
1265
1266 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci)
1267 {
1268 struct mlxsw_pci_mem_item *mem_item;
1269 int i;
1270
1271 mlxsw_cmd_unmap_fa(mlxsw_pci->core);
1272
1273 for (i = 0; i < mlxsw_pci->fw_area.count; i++) {
1274 mem_item = &mlxsw_pci->fw_area.items[i];
1275
1276 pci_free_consistent(mlxsw_pci->pdev, mem_item->size,
1277 mem_item->buf, mem_item->mapaddr);
1278 }
1279 kfree(mlxsw_pci->fw_area.items);
1280 }
1281
1282 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id)
1283 {
1284 struct mlxsw_pci *mlxsw_pci = dev_id;
1285 struct mlxsw_pci_queue *q;
1286 int i;
1287
1288 for (i = 0; i < MLXSW_PCI_EQS_COUNT; i++) {
1289 q = mlxsw_pci_eq_get(mlxsw_pci, i);
1290 mlxsw_pci_queue_tasklet_schedule(q);
1291 }
1292 return IRQ_HANDLED;
1293 }
1294
1295 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci,
1296 struct mlxsw_pci_mem_item *mbox)
1297 {
1298 struct pci_dev *pdev = mlxsw_pci->pdev;
1299 int err = 0;
1300
1301 mbox->size = MLXSW_CMD_MBOX_SIZE;
1302 mbox->buf = pci_alloc_consistent(pdev, MLXSW_CMD_MBOX_SIZE,
1303 &mbox->mapaddr);
1304 if (!mbox->buf) {
1305 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n");
1306 err = -ENOMEM;
1307 }
1308
1309 return err;
1310 }
1311
1312 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci,
1313 struct mlxsw_pci_mem_item *mbox)
1314 {
1315 struct pci_dev *pdev = mlxsw_pci->pdev;
1316
1317 pci_free_consistent(pdev, MLXSW_CMD_MBOX_SIZE, mbox->buf,
1318 mbox->mapaddr);
1319 }
1320
1321 static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci,
1322 const struct pci_device_id *id,
1323 u32 *p_sys_status)
1324 {
1325 unsigned long end;
1326 u32 val;
1327
1328 if (id->device == PCI_DEVICE_ID_MELLANOX_SWITCHX2) {
1329 msleep(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1330 return 0;
1331 }
1332
1333
1334 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS);
1335
1336 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS);
1337 do {
1338 val = mlxsw_pci_read32(mlxsw_pci, FW_READY);
1339 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC)
1340 return 0;
1341 cond_resched();
1342 } while (time_before(jiffies, end));
1343
1344 *p_sys_status = val & MLXSW_PCI_FW_READY_MASK;
1345
1346 return -EBUSY;
1347 }
1348
1349 static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci,
1350 const struct pci_device_id *id)
1351 {
1352 struct pci_dev *pdev = mlxsw_pci->pdev;
1353 char mrsr_pl[MLXSW_REG_MRSR_LEN];
1354 u32 sys_status;
1355 int err;
1356
1357 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1358 if (err) {
1359 dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n",
1360 sys_status);
1361 return err;
1362 }
1363
1364 mlxsw_reg_mrsr_pack(mrsr_pl);
1365 err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl);
1366 if (err)
1367 return err;
1368
1369 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status);
1370 if (err) {
1371 dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n",
1372 sys_status);
1373 return err;
1374 }
1375
1376 return 0;
1377 }
1378
1379 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1380 {
1381 int err;
1382
1383 err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX);
1384 if (err < 0)
1385 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n");
1386 return err;
1387 }
1388
1389 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci)
1390 {
1391 pci_free_irq_vectors(mlxsw_pci->pdev);
1392 }
1393
1394 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
1395 const struct mlxsw_config_profile *profile,
1396 struct mlxsw_res *res)
1397 {
1398 struct mlxsw_pci *mlxsw_pci = bus_priv;
1399 struct pci_dev *pdev = mlxsw_pci->pdev;
1400 char *mbox;
1401 u16 num_pages;
1402 int err;
1403
1404 mutex_init(&mlxsw_pci->cmd.lock);
1405 init_waitqueue_head(&mlxsw_pci->cmd.wait);
1406
1407 mlxsw_pci->core = mlxsw_core;
1408
1409 mbox = mlxsw_cmd_mbox_alloc();
1410 if (!mbox)
1411 return -ENOMEM;
1412
1413 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1414 if (err)
1415 goto mbox_put;
1416
1417 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1418 if (err)
1419 goto err_out_mbox_alloc;
1420
1421 err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id);
1422 if (err)
1423 goto err_sw_reset;
1424
1425 err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci);
1426 if (err < 0) {
1427 dev_err(&pdev->dev, "MSI-X init failed\n");
1428 goto err_alloc_irq;
1429 }
1430
1431 err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
1432 if (err)
1433 goto err_query_fw;
1434
1435 mlxsw_pci->bus_info.fw_rev.major =
1436 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
1437 mlxsw_pci->bus_info.fw_rev.minor =
1438 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
1439 mlxsw_pci->bus_info.fw_rev.subminor =
1440 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
1441
1442 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {
1443 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n");
1444 err = -EINVAL;
1445 goto err_iface_rev;
1446 }
1447 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {
1448 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n");
1449 err = -EINVAL;
1450 goto err_doorbell_page_bar;
1451 }
1452
1453 mlxsw_pci->doorbell_offset =
1454 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
1455
1456 if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) {
1457 dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n");
1458 err = -EINVAL;
1459 goto err_fr_rn_clk_bar;
1460 }
1461
1462 mlxsw_pci->free_running_clock_offset =
1463 mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);
1464
1465 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
1466 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
1467 if (err)
1468 goto err_fw_area_init;
1469
1470 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);
1471 if (err)
1472 goto err_boardinfo;
1473
1474 err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
1475 if (err)
1476 goto err_query_resources;
1477
1478 if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) &&
1479 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2))
1480 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2;
1481 else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) &&
1482 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1))
1483 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1;
1484 else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) &&
1485 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) ||
1486 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) {
1487 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0;
1488 } else {
1489 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n");
1490 goto err_cqe_v_check;
1491 }
1492
1493 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);
1494 if (err)
1495 goto err_config_profile;
1496
1497 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);
1498 if (err)
1499 goto err_aqs_init;
1500
1501 err = request_irq(pci_irq_vector(pdev, 0),
1502 mlxsw_pci_eq_irq_handler, 0,
1503 mlxsw_pci->bus_info.device_kind, mlxsw_pci);
1504 if (err) {
1505 dev_err(&pdev->dev, "IRQ request failed\n");
1506 goto err_request_eq_irq;
1507 }
1508
1509 goto mbox_put;
1510
1511 err_request_eq_irq:
1512 mlxsw_pci_aqs_fini(mlxsw_pci);
1513 err_aqs_init:
1514 err_config_profile:
1515 err_cqe_v_check:
1516 err_query_resources:
1517 err_boardinfo:
1518 mlxsw_pci_fw_area_fini(mlxsw_pci);
1519 err_fw_area_init:
1520 err_fr_rn_clk_bar:
1521 err_doorbell_page_bar:
1522 err_iface_rev:
1523 err_query_fw:
1524 mlxsw_pci_free_irq_vectors(mlxsw_pci);
1525 err_alloc_irq:
1526 err_sw_reset:
1527 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1528 err_out_mbox_alloc:
1529 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1530 mbox_put:
1531 mlxsw_cmd_mbox_free(mbox);
1532 return err;
1533 }
1534
1535 static void mlxsw_pci_fini(void *bus_priv)
1536 {
1537 struct mlxsw_pci *mlxsw_pci = bus_priv;
1538
1539 free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci);
1540 mlxsw_pci_aqs_fini(mlxsw_pci);
1541 mlxsw_pci_fw_area_fini(mlxsw_pci);
1542 mlxsw_pci_free_irq_vectors(mlxsw_pci);
1543 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox);
1544 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox);
1545 }
1546
1547 static struct mlxsw_pci_queue *
1548 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci,
1549 const struct mlxsw_tx_info *tx_info)
1550 {
1551 u8 sdqn = tx_info->local_port % mlxsw_pci_sdq_count(mlxsw_pci);
1552
1553 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn);
1554 }
1555
1556 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv,
1557 const struct mlxsw_tx_info *tx_info)
1558 {
1559 struct mlxsw_pci *mlxsw_pci = bus_priv;
1560 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1561
1562 return !mlxsw_pci_queue_elem_info_producer_get(q);
1563 }
1564
1565 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb,
1566 const struct mlxsw_tx_info *tx_info)
1567 {
1568 struct mlxsw_pci *mlxsw_pci = bus_priv;
1569 struct mlxsw_pci_queue *q;
1570 struct mlxsw_pci_queue_elem_info *elem_info;
1571 char *wqe;
1572 int i;
1573 int err;
1574
1575 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) {
1576 err = skb_linearize(skb);
1577 if (err)
1578 return err;
1579 }
1580
1581 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info);
1582 spin_lock_bh(&q->lock);
1583 elem_info = mlxsw_pci_queue_elem_info_producer_get(q);
1584 if (!elem_info) {
1585
1586 err = -EAGAIN;
1587 goto unlock;
1588 }
1589 mlxsw_skb_cb(skb)->tx_info = *tx_info;
1590 elem_info->u.sdq.skb = skb;
1591
1592 wqe = elem_info->elem;
1593 mlxsw_pci_wqe_c_set(wqe, 1);
1594 mlxsw_pci_wqe_lp_set(wqe, !!tx_info->is_emad);
1595 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET);
1596
1597 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data,
1598 skb_headlen(skb), DMA_TO_DEVICE);
1599 if (err)
1600 goto unlock;
1601
1602 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1603 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1604
1605 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1,
1606 skb_frag_address(frag),
1607 skb_frag_size(frag),
1608 DMA_TO_DEVICE);
1609 if (err)
1610 goto unmap_frags;
1611 }
1612
1613 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
1614 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1615
1616
1617 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++)
1618 mlxsw_pci_wqe_byte_count_set(wqe, i, 0);
1619
1620
1621 q->producer_counter++;
1622 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q);
1623
1624 goto unlock;
1625
1626 unmap_frags:
1627 for (; i >= 0; i--)
1628 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE);
1629 unlock:
1630 spin_unlock_bh(&q->lock);
1631 return err;
1632 }
1633
1634 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
1635 u32 in_mod, bool out_mbox_direct,
1636 char *in_mbox, size_t in_mbox_size,
1637 char *out_mbox, size_t out_mbox_size,
1638 u8 *p_status)
1639 {
1640 struct mlxsw_pci *mlxsw_pci = bus_priv;
1641 dma_addr_t in_mapaddr = 0, out_mapaddr = 0;
1642 bool evreq = mlxsw_pci->cmd.nopoll;
1643 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS);
1644 bool *p_wait_done = &mlxsw_pci->cmd.wait_done;
1645 int err;
1646
1647 *p_status = MLXSW_CMD_STATUS_OK;
1648
1649 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock);
1650 if (err)
1651 return err;
1652
1653 if (in_mbox) {
1654 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size);
1655 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr;
1656 }
1657 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr));
1658 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr));
1659
1660 if (out_mbox)
1661 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr;
1662 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr));
1663 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr));
1664
1665 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod);
1666 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0);
1667
1668 *p_wait_done = false;
1669
1670 wmb();
1671 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL,
1672 MLXSW_PCI_CIR_CTRL_GO_BIT |
1673 (evreq ? MLXSW_PCI_CIR_CTRL_EVREQ_BIT : 0) |
1674 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) |
1675 opcode);
1676
1677 if (!evreq) {
1678 unsigned long end;
1679
1680 end = jiffies + timeout;
1681 do {
1682 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL);
1683
1684 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) {
1685 *p_wait_done = true;
1686 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT;
1687 break;
1688 }
1689 cond_resched();
1690 } while (time_before(jiffies, end));
1691 } else {
1692 wait_event_timeout(mlxsw_pci->cmd.wait, *p_wait_done, timeout);
1693 *p_status = mlxsw_pci->cmd.comp.status;
1694 }
1695
1696 err = 0;
1697 if (*p_wait_done) {
1698 if (*p_status)
1699 err = -EIO;
1700 } else {
1701 err = -ETIMEDOUT;
1702 }
1703
1704 if (!err && out_mbox && out_mbox_direct) {
1705
1706
1707
1708
1709 __be32 tmp;
1710
1711 if (!evreq) {
1712 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1713 CIR_OUT_PARAM_HI));
1714 memcpy(out_mbox, &tmp, sizeof(tmp));
1715 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci,
1716 CIR_OUT_PARAM_LO));
1717 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp));
1718 }
1719 } else if (!err && out_mbox) {
1720 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size);
1721 }
1722
1723 mutex_unlock(&mlxsw_pci->cmd.lock);
1724
1725 return err;
1726 }
1727
1728 static u32 mlxsw_pci_read_frc_h(void *bus_priv)
1729 {
1730 struct mlxsw_pci *mlxsw_pci = bus_priv;
1731 u64 frc_offset;
1732
1733 frc_offset = mlxsw_pci->free_running_clock_offset;
1734 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset));
1735 }
1736
1737 static u32 mlxsw_pci_read_frc_l(void *bus_priv)
1738 {
1739 struct mlxsw_pci *mlxsw_pci = bus_priv;
1740 u64 frc_offset;
1741
1742 frc_offset = mlxsw_pci->free_running_clock_offset;
1743 return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset));
1744 }
1745
1746 static const struct mlxsw_bus mlxsw_pci_bus = {
1747 .kind = "pci",
1748 .init = mlxsw_pci_init,
1749 .fini = mlxsw_pci_fini,
1750 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy,
1751 .skb_transmit = mlxsw_pci_skb_transmit,
1752 .cmd_exec = mlxsw_pci_cmd_exec,
1753 .read_frc_h = mlxsw_pci_read_frc_h,
1754 .read_frc_l = mlxsw_pci_read_frc_l,
1755 .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
1756 };
1757
1758 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1759 {
1760 const char *driver_name = pdev->driver->name;
1761 struct mlxsw_pci *mlxsw_pci;
1762 int err;
1763
1764 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL);
1765 if (!mlxsw_pci)
1766 return -ENOMEM;
1767
1768 err = pci_enable_device(pdev);
1769 if (err) {
1770 dev_err(&pdev->dev, "pci_enable_device failed\n");
1771 goto err_pci_enable_device;
1772 }
1773
1774 err = pci_request_regions(pdev, driver_name);
1775 if (err) {
1776 dev_err(&pdev->dev, "pci_request_regions failed\n");
1777 goto err_pci_request_regions;
1778 }
1779
1780 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1781 if (!err) {
1782 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1783 if (err) {
1784 dev_err(&pdev->dev, "pci_set_consistent_dma_mask failed\n");
1785 goto err_pci_set_dma_mask;
1786 }
1787 } else {
1788 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1789 if (err) {
1790 dev_err(&pdev->dev, "pci_set_dma_mask failed\n");
1791 goto err_pci_set_dma_mask;
1792 }
1793 }
1794
1795 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) {
1796 dev_err(&pdev->dev, "invalid PCI region size\n");
1797 err = -EINVAL;
1798 goto err_pci_resource_len_check;
1799 }
1800
1801 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0),
1802 pci_resource_len(pdev, 0));
1803 if (!mlxsw_pci->hw_addr) {
1804 dev_err(&pdev->dev, "ioremap failed\n");
1805 err = -EIO;
1806 goto err_ioremap;
1807 }
1808 pci_set_master(pdev);
1809
1810 mlxsw_pci->pdev = pdev;
1811 pci_set_drvdata(pdev, mlxsw_pci);
1812
1813 mlxsw_pci->bus_info.device_kind = driver_name;
1814 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
1815 mlxsw_pci->bus_info.dev = &pdev->dev;
1816 mlxsw_pci->bus_info.read_frc_capable = true;
1817 mlxsw_pci->id = id;
1818
1819 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,
1820 &mlxsw_pci_bus, mlxsw_pci, false,
1821 NULL);
1822 if (err) {
1823 dev_err(&pdev->dev, "cannot register bus device\n");
1824 goto err_bus_device_register;
1825 }
1826
1827 return 0;
1828
1829 err_bus_device_register:
1830 iounmap(mlxsw_pci->hw_addr);
1831 err_ioremap:
1832 err_pci_resource_len_check:
1833 err_pci_set_dma_mask:
1834 pci_release_regions(pdev);
1835 err_pci_request_regions:
1836 pci_disable_device(pdev);
1837 err_pci_enable_device:
1838 kfree(mlxsw_pci);
1839 return err;
1840 }
1841
1842 static void mlxsw_pci_remove(struct pci_dev *pdev)
1843 {
1844 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev);
1845
1846 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false);
1847 iounmap(mlxsw_pci->hw_addr);
1848 pci_release_regions(mlxsw_pci->pdev);
1849 pci_disable_device(mlxsw_pci->pdev);
1850 kfree(mlxsw_pci);
1851 }
1852
1853 int mlxsw_pci_driver_register(struct pci_driver *pci_driver)
1854 {
1855 pci_driver->probe = mlxsw_pci_probe;
1856 pci_driver->remove = mlxsw_pci_remove;
1857 return pci_register_driver(pci_driver);
1858 }
1859 EXPORT_SYMBOL(mlxsw_pci_driver_register);
1860
1861 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver)
1862 {
1863 pci_unregister_driver(pci_driver);
1864 }
1865 EXPORT_SYMBOL(mlxsw_pci_driver_unregister);
1866
1867 static int __init mlxsw_pci_module_init(void)
1868 {
1869 return 0;
1870 }
1871
1872 static void __exit mlxsw_pci_module_exit(void)
1873 {
1874 }
1875
1876 module_init(mlxsw_pci_module_init);
1877 module_exit(mlxsw_pci_module_exit);
1878
1879 MODULE_LICENSE("Dual BSD/GPL");
1880 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1881 MODULE_DESCRIPTION("Mellanox switch PCI interface driver");