This source file includes following definitions.
- i40e_set_mac_type
- i40e_aq_str
- i40e_stat_str
- i40e_debug_aq
- i40e_check_asq_alive
- i40e_aq_queue_shutdown
- i40e_aq_get_set_rss_lut
- i40e_aq_get_rss_lut
- i40e_aq_set_rss_lut
- i40e_aq_get_set_rss_key
- i40e_aq_get_rss_key
- i40e_aq_set_rss_key
- i40e_init_shared_code
- i40e_aq_mac_address_read
- i40e_aq_mac_address_write
- i40e_get_mac_addr
- i40e_get_port_mac_addr
- i40e_pre_tx_queue_cfg
- i40e_read_pba_string
- i40e_get_media_type
- i40e_poll_globr
- i40e_pf_reset
- i40e_clear_hw
- i40e_clear_pxe_mode
- i40e_led_is_mine
- i40e_led_get
- i40e_led_set
- i40e_aq_get_phy_capabilities
- i40e_aq_set_phy_config
- i40e_set_fc_status
- i40e_set_fc
- i40e_aq_clear_pxe_mode
- i40e_aq_set_link_restart_an
- i40e_aq_get_link_info
- i40e_aq_set_phy_int_mask
- i40e_aq_set_phy_debug
- i40e_aq_add_vsi
- i40e_aq_set_default_vsi
- i40e_aq_clear_default_vsi
- i40e_aq_set_vsi_unicast_promiscuous
- i40e_aq_set_vsi_multicast_promiscuous
- i40e_aq_set_vsi_mc_promisc_on_vlan
- i40e_aq_set_vsi_uc_promisc_on_vlan
- i40e_aq_set_vsi_bc_promisc_on_vlan
- i40e_aq_set_vsi_broadcast
- i40e_aq_set_vsi_vlan_promisc
- i40e_aq_get_vsi_params
- i40e_aq_update_vsi_params
- i40e_aq_get_switch_config
- i40e_aq_set_switch_config
- i40e_aq_get_firmware_version
- i40e_aq_send_driver_version
- i40e_get_link_status
- i40e_update_link_info
- i40e_aq_add_veb
- i40e_aq_get_veb_parameters
- i40e_aq_add_macvlan
- i40e_aq_remove_macvlan
- i40e_mirrorrule_op
- i40e_aq_add_mirrorrule
- i40e_aq_delete_mirrorrule
- i40e_aq_send_msg_to_vf
- i40e_aq_debug_read_register
- i40e_aq_debug_write_register
- i40e_aq_request_resource
- i40e_aq_release_resource
- i40e_aq_read_nvm
- i40e_aq_erase_nvm
- i40e_parse_discover_capabilities
- i40e_aq_discover_capabilities
- i40e_aq_update_nvm
- i40e_aq_rearrange_nvm
- i40e_aq_get_lldp_mib
- i40e_aq_cfg_lldp_mib_change_event
- i40e_aq_restore_lldp
- i40e_aq_stop_lldp
- i40e_aq_start_lldp
- i40e_aq_set_dcb_parameters
- i40e_aq_get_cee_dcb_config
- i40e_aq_add_udp_tunnel
- i40e_aq_del_udp_tunnel
- i40e_aq_delete_element
- i40e_aq_dcb_updated
- i40e_aq_tx_sched_cmd
- i40e_aq_config_vsi_bw_limit
- i40e_aq_config_vsi_tc_bw
- i40e_aq_config_switch_comp_ets
- i40e_aq_config_switch_comp_bw_config
- i40e_aq_query_vsi_bw_config
- i40e_aq_query_vsi_ets_sla_config
- i40e_aq_query_switch_comp_ets_config
- i40e_aq_query_port_ets_config
- i40e_aq_query_switch_comp_bw_config
- i40e_validate_filter_settings
- i40e_set_filter_control
- i40e_aq_add_rem_control_packet_filter
- i40e_add_filter_to_drop_tx_flow_control_frames
- i40e_aq_alternate_read
- i40e_aq_resume_port_tx
- i40e_set_pci_config_data
- i40e_aq_debug_dump
- i40e_read_bw_from_alt_ram
- i40e_aq_configure_partition_bw
- i40e_read_phy_register_clause22
- i40e_write_phy_register_clause22
- i40e_read_phy_register_clause45
- i40e_write_phy_register_clause45
- i40e_write_phy_register
- i40e_read_phy_register
- i40e_get_phy_address
- i40e_blink_phy_link_led
- i40e_led_get_reg
- i40e_led_set_reg
- i40e_led_get_phy
- i40e_led_set_phy
- i40e_aq_rx_ctl_read_register
- i40e_read_rx_ctl
- i40e_aq_rx_ctl_write_register
- i40e_write_rx_ctl
- i40e_aq_set_phy_register
- i40e_aq_get_phy_register
- i40e_aq_write_ddp
- i40e_aq_get_ddp_list
- i40e_find_segment_in_package
- i40e_find_section_in_profile
- i40e_ddp_exec_aq_section
- i40e_validate_profile
- i40e_write_profile
- i40e_rollback_profile
- i40e_add_pinfo_to_list
- i40e_aq_add_cloud_filters
- i40e_aq_add_cloud_filters_bb
- i40e_aq_rem_cloud_filters
- i40e_aq_rem_cloud_filters_bb
1
2
3
4 #include "i40e.h"
5 #include "i40e_type.h"
6 #include "i40e_adminq.h"
7 #include "i40e_prototype.h"
8 #include <linux/avf/virtchnl.h>
9
10
11
12
13
14
15
16
17 i40e_status i40e_set_mac_type(struct i40e_hw *hw)
18 {
19 i40e_status status = 0;
20
21 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
22 switch (hw->device_id) {
23 case I40E_DEV_ID_SFP_XL710:
24 case I40E_DEV_ID_QEMU:
25 case I40E_DEV_ID_KX_B:
26 case I40E_DEV_ID_KX_C:
27 case I40E_DEV_ID_QSFP_A:
28 case I40E_DEV_ID_QSFP_B:
29 case I40E_DEV_ID_QSFP_C:
30 case I40E_DEV_ID_10G_BASE_T:
31 case I40E_DEV_ID_10G_BASE_T4:
32 case I40E_DEV_ID_10G_B:
33 case I40E_DEV_ID_10G_SFP:
34 case I40E_DEV_ID_20G_KR2:
35 case I40E_DEV_ID_20G_KR2_A:
36 case I40E_DEV_ID_25G_B:
37 case I40E_DEV_ID_25G_SFP28:
38 case I40E_DEV_ID_X710_N3000:
39 case I40E_DEV_ID_XXV710_N3000:
40 hw->mac.type = I40E_MAC_XL710;
41 break;
42 case I40E_DEV_ID_KX_X722:
43 case I40E_DEV_ID_QSFP_X722:
44 case I40E_DEV_ID_SFP_X722:
45 case I40E_DEV_ID_1G_BASE_T_X722:
46 case I40E_DEV_ID_10G_BASE_T_X722:
47 case I40E_DEV_ID_SFP_I_X722:
48 hw->mac.type = I40E_MAC_X722;
49 break;
50 default:
51 hw->mac.type = I40E_MAC_GENERIC;
52 break;
53 }
54 } else {
55 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
56 }
57
58 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
59 hw->mac.type, status);
60 return status;
61 }
62
63
64
65
66
67
68 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
69 {
70 switch (aq_err) {
71 case I40E_AQ_RC_OK:
72 return "OK";
73 case I40E_AQ_RC_EPERM:
74 return "I40E_AQ_RC_EPERM";
75 case I40E_AQ_RC_ENOENT:
76 return "I40E_AQ_RC_ENOENT";
77 case I40E_AQ_RC_ESRCH:
78 return "I40E_AQ_RC_ESRCH";
79 case I40E_AQ_RC_EINTR:
80 return "I40E_AQ_RC_EINTR";
81 case I40E_AQ_RC_EIO:
82 return "I40E_AQ_RC_EIO";
83 case I40E_AQ_RC_ENXIO:
84 return "I40E_AQ_RC_ENXIO";
85 case I40E_AQ_RC_E2BIG:
86 return "I40E_AQ_RC_E2BIG";
87 case I40E_AQ_RC_EAGAIN:
88 return "I40E_AQ_RC_EAGAIN";
89 case I40E_AQ_RC_ENOMEM:
90 return "I40E_AQ_RC_ENOMEM";
91 case I40E_AQ_RC_EACCES:
92 return "I40E_AQ_RC_EACCES";
93 case I40E_AQ_RC_EFAULT:
94 return "I40E_AQ_RC_EFAULT";
95 case I40E_AQ_RC_EBUSY:
96 return "I40E_AQ_RC_EBUSY";
97 case I40E_AQ_RC_EEXIST:
98 return "I40E_AQ_RC_EEXIST";
99 case I40E_AQ_RC_EINVAL:
100 return "I40E_AQ_RC_EINVAL";
101 case I40E_AQ_RC_ENOTTY:
102 return "I40E_AQ_RC_ENOTTY";
103 case I40E_AQ_RC_ENOSPC:
104 return "I40E_AQ_RC_ENOSPC";
105 case I40E_AQ_RC_ENOSYS:
106 return "I40E_AQ_RC_ENOSYS";
107 case I40E_AQ_RC_ERANGE:
108 return "I40E_AQ_RC_ERANGE";
109 case I40E_AQ_RC_EFLUSHED:
110 return "I40E_AQ_RC_EFLUSHED";
111 case I40E_AQ_RC_BAD_ADDR:
112 return "I40E_AQ_RC_BAD_ADDR";
113 case I40E_AQ_RC_EMODE:
114 return "I40E_AQ_RC_EMODE";
115 case I40E_AQ_RC_EFBIG:
116 return "I40E_AQ_RC_EFBIG";
117 }
118
119 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
120 return hw->err_str;
121 }
122
123
124
125
126
127
128 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
129 {
130 switch (stat_err) {
131 case 0:
132 return "OK";
133 case I40E_ERR_NVM:
134 return "I40E_ERR_NVM";
135 case I40E_ERR_NVM_CHECKSUM:
136 return "I40E_ERR_NVM_CHECKSUM";
137 case I40E_ERR_PHY:
138 return "I40E_ERR_PHY";
139 case I40E_ERR_CONFIG:
140 return "I40E_ERR_CONFIG";
141 case I40E_ERR_PARAM:
142 return "I40E_ERR_PARAM";
143 case I40E_ERR_MAC_TYPE:
144 return "I40E_ERR_MAC_TYPE";
145 case I40E_ERR_UNKNOWN_PHY:
146 return "I40E_ERR_UNKNOWN_PHY";
147 case I40E_ERR_LINK_SETUP:
148 return "I40E_ERR_LINK_SETUP";
149 case I40E_ERR_ADAPTER_STOPPED:
150 return "I40E_ERR_ADAPTER_STOPPED";
151 case I40E_ERR_INVALID_MAC_ADDR:
152 return "I40E_ERR_INVALID_MAC_ADDR";
153 case I40E_ERR_DEVICE_NOT_SUPPORTED:
154 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
155 case I40E_ERR_MASTER_REQUESTS_PENDING:
156 return "I40E_ERR_MASTER_REQUESTS_PENDING";
157 case I40E_ERR_INVALID_LINK_SETTINGS:
158 return "I40E_ERR_INVALID_LINK_SETTINGS";
159 case I40E_ERR_AUTONEG_NOT_COMPLETE:
160 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
161 case I40E_ERR_RESET_FAILED:
162 return "I40E_ERR_RESET_FAILED";
163 case I40E_ERR_SWFW_SYNC:
164 return "I40E_ERR_SWFW_SYNC";
165 case I40E_ERR_NO_AVAILABLE_VSI:
166 return "I40E_ERR_NO_AVAILABLE_VSI";
167 case I40E_ERR_NO_MEMORY:
168 return "I40E_ERR_NO_MEMORY";
169 case I40E_ERR_BAD_PTR:
170 return "I40E_ERR_BAD_PTR";
171 case I40E_ERR_RING_FULL:
172 return "I40E_ERR_RING_FULL";
173 case I40E_ERR_INVALID_PD_ID:
174 return "I40E_ERR_INVALID_PD_ID";
175 case I40E_ERR_INVALID_QP_ID:
176 return "I40E_ERR_INVALID_QP_ID";
177 case I40E_ERR_INVALID_CQ_ID:
178 return "I40E_ERR_INVALID_CQ_ID";
179 case I40E_ERR_INVALID_CEQ_ID:
180 return "I40E_ERR_INVALID_CEQ_ID";
181 case I40E_ERR_INVALID_AEQ_ID:
182 return "I40E_ERR_INVALID_AEQ_ID";
183 case I40E_ERR_INVALID_SIZE:
184 return "I40E_ERR_INVALID_SIZE";
185 case I40E_ERR_INVALID_ARP_INDEX:
186 return "I40E_ERR_INVALID_ARP_INDEX";
187 case I40E_ERR_INVALID_FPM_FUNC_ID:
188 return "I40E_ERR_INVALID_FPM_FUNC_ID";
189 case I40E_ERR_QP_INVALID_MSG_SIZE:
190 return "I40E_ERR_QP_INVALID_MSG_SIZE";
191 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
192 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
193 case I40E_ERR_INVALID_FRAG_COUNT:
194 return "I40E_ERR_INVALID_FRAG_COUNT";
195 case I40E_ERR_QUEUE_EMPTY:
196 return "I40E_ERR_QUEUE_EMPTY";
197 case I40E_ERR_INVALID_ALIGNMENT:
198 return "I40E_ERR_INVALID_ALIGNMENT";
199 case I40E_ERR_FLUSHED_QUEUE:
200 return "I40E_ERR_FLUSHED_QUEUE";
201 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
202 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
203 case I40E_ERR_INVALID_IMM_DATA_SIZE:
204 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
205 case I40E_ERR_TIMEOUT:
206 return "I40E_ERR_TIMEOUT";
207 case I40E_ERR_OPCODE_MISMATCH:
208 return "I40E_ERR_OPCODE_MISMATCH";
209 case I40E_ERR_CQP_COMPL_ERROR:
210 return "I40E_ERR_CQP_COMPL_ERROR";
211 case I40E_ERR_INVALID_VF_ID:
212 return "I40E_ERR_INVALID_VF_ID";
213 case I40E_ERR_INVALID_HMCFN_ID:
214 return "I40E_ERR_INVALID_HMCFN_ID";
215 case I40E_ERR_BACKING_PAGE_ERROR:
216 return "I40E_ERR_BACKING_PAGE_ERROR";
217 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
218 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
219 case I40E_ERR_INVALID_PBLE_INDEX:
220 return "I40E_ERR_INVALID_PBLE_INDEX";
221 case I40E_ERR_INVALID_SD_INDEX:
222 return "I40E_ERR_INVALID_SD_INDEX";
223 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
224 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
225 case I40E_ERR_INVALID_SD_TYPE:
226 return "I40E_ERR_INVALID_SD_TYPE";
227 case I40E_ERR_MEMCPY_FAILED:
228 return "I40E_ERR_MEMCPY_FAILED";
229 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
230 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
231 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
232 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
233 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
234 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
235 case I40E_ERR_SRQ_ENABLED:
236 return "I40E_ERR_SRQ_ENABLED";
237 case I40E_ERR_ADMIN_QUEUE_ERROR:
238 return "I40E_ERR_ADMIN_QUEUE_ERROR";
239 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
240 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
241 case I40E_ERR_BUF_TOO_SHORT:
242 return "I40E_ERR_BUF_TOO_SHORT";
243 case I40E_ERR_ADMIN_QUEUE_FULL:
244 return "I40E_ERR_ADMIN_QUEUE_FULL";
245 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
246 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
247 case I40E_ERR_BAD_IWARP_CQE:
248 return "I40E_ERR_BAD_IWARP_CQE";
249 case I40E_ERR_NVM_BLANK_MODE:
250 return "I40E_ERR_NVM_BLANK_MODE";
251 case I40E_ERR_NOT_IMPLEMENTED:
252 return "I40E_ERR_NOT_IMPLEMENTED";
253 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
254 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
255 case I40E_ERR_DIAG_TEST_FAILED:
256 return "I40E_ERR_DIAG_TEST_FAILED";
257 case I40E_ERR_NOT_READY:
258 return "I40E_ERR_NOT_READY";
259 case I40E_NOT_SUPPORTED:
260 return "I40E_NOT_SUPPORTED";
261 case I40E_ERR_FIRMWARE_API_VERSION:
262 return "I40E_ERR_FIRMWARE_API_VERSION";
263 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
264 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
265 }
266
267 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
268 return hw->err_str;
269 }
270
271
272
273
274
275
276
277
278
279
280
281 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
282 void *buffer, u16 buf_len)
283 {
284 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
285 u32 effective_mask = hw->debug_mask & mask;
286 char prefix[27];
287 u16 len;
288 u8 *buf = (u8 *)buffer;
289
290 if (!effective_mask || !desc)
291 return;
292
293 len = le16_to_cpu(aq_desc->datalen);
294
295 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
296 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
297 le16_to_cpu(aq_desc->opcode),
298 le16_to_cpu(aq_desc->flags),
299 le16_to_cpu(aq_desc->datalen),
300 le16_to_cpu(aq_desc->retval));
301 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
302 "\tcookie (h,l) 0x%08X 0x%08X\n",
303 le32_to_cpu(aq_desc->cookie_high),
304 le32_to_cpu(aq_desc->cookie_low));
305 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
306 "\tparam (0,1) 0x%08X 0x%08X\n",
307 le32_to_cpu(aq_desc->params.internal.param0),
308 le32_to_cpu(aq_desc->params.internal.param1));
309 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
310 "\taddr (h,l) 0x%08X 0x%08X\n",
311 le32_to_cpu(aq_desc->params.external.addr_high),
312 le32_to_cpu(aq_desc->params.external.addr_low));
313
314 if (buffer && buf_len != 0 && len != 0 &&
315 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
316 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
317 if (buf_len < len)
318 len = buf_len;
319
320 snprintf(prefix, sizeof(prefix),
321 "i40e %02x:%02x.%x: \t0x",
322 hw->bus.bus_id,
323 hw->bus.device,
324 hw->bus.func);
325
326 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
327 16, 1, buf, len, false);
328 }
329 }
330
331
332
333
334
335
336
337 bool i40e_check_asq_alive(struct i40e_hw *hw)
338 {
339 if (hw->aq.asq.len)
340 return !!(rd32(hw, hw->aq.asq.len) &
341 I40E_PF_ATQLEN_ATQENABLE_MASK);
342 else
343 return false;
344 }
345
346
347
348
349
350
351
352
353
354 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
355 bool unloading)
356 {
357 struct i40e_aq_desc desc;
358 struct i40e_aqc_queue_shutdown *cmd =
359 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
360 i40e_status status;
361
362 i40e_fill_default_direct_cmd_desc(&desc,
363 i40e_aqc_opc_queue_shutdown);
364
365 if (unloading)
366 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
367 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
368
369 return status;
370 }
371
372
373
374
375
376
377
378
379
380
381
382
383 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
384 u16 vsi_id, bool pf_lut,
385 u8 *lut, u16 lut_size,
386 bool set)
387 {
388 i40e_status status;
389 struct i40e_aq_desc desc;
390 struct i40e_aqc_get_set_rss_lut *cmd_resp =
391 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
392
393 if (set)
394 i40e_fill_default_direct_cmd_desc(&desc,
395 i40e_aqc_opc_set_rss_lut);
396 else
397 i40e_fill_default_direct_cmd_desc(&desc,
398 i40e_aqc_opc_get_rss_lut);
399
400
401 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
402 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
403
404 cmd_resp->vsi_id =
405 cpu_to_le16((u16)((vsi_id <<
406 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
407 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
408 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
409
410 if (pf_lut)
411 cmd_resp->flags |= cpu_to_le16((u16)
412 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
413 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
414 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
415 else
416 cmd_resp->flags |= cpu_to_le16((u16)
417 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
419 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
420
421 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
422
423 return status;
424 }
425
426
427
428
429
430
431
432
433
434
435
436 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
437 bool pf_lut, u8 *lut, u16 lut_size)
438 {
439 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
440 false);
441 }
442
443
444
445
446
447
448
449
450
451
452
453 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
454 bool pf_lut, u8 *lut, u16 lut_size)
455 {
456 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
457 }
458
459
460
461
462
463
464
465
466
467
468 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
469 u16 vsi_id,
470 struct i40e_aqc_get_set_rss_key_data *key,
471 bool set)
472 {
473 i40e_status status;
474 struct i40e_aq_desc desc;
475 struct i40e_aqc_get_set_rss_key *cmd_resp =
476 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
477 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
478
479 if (set)
480 i40e_fill_default_direct_cmd_desc(&desc,
481 i40e_aqc_opc_set_rss_key);
482 else
483 i40e_fill_default_direct_cmd_desc(&desc,
484 i40e_aqc_opc_get_rss_key);
485
486
487 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
488 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
489
490 cmd_resp->vsi_id =
491 cpu_to_le16((u16)((vsi_id <<
492 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
493 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
494 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
495
496 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
497
498 return status;
499 }
500
501
502
503
504
505
506
507
508 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
509 u16 vsi_id,
510 struct i40e_aqc_get_set_rss_key_data *key)
511 {
512 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
513 }
514
515
516
517
518
519
520
521
522
523 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
524 u16 vsi_id,
525 struct i40e_aqc_get_set_rss_key_data *key)
526 {
527 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
528 }
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
555 { PTYPE, \
556 1, \
557 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
558 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
559 I40E_RX_PTYPE_##OUTER_FRAG, \
560 I40E_RX_PTYPE_TUNNEL_##T, \
561 I40E_RX_PTYPE_TUNNEL_END_##TE, \
562 I40E_RX_PTYPE_##TEF, \
563 I40E_RX_PTYPE_INNER_PROT_##I, \
564 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
565
566 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
567 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
568
569
570 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
571 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
572 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
573
574
575 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
576
577 I40E_PTT_UNUSED_ENTRY(0),
578 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
579 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
580 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
581 I40E_PTT_UNUSED_ENTRY(4),
582 I40E_PTT_UNUSED_ENTRY(5),
583 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
584 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT_UNUSED_ENTRY(8),
586 I40E_PTT_UNUSED_ENTRY(9),
587 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
588 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
589 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
590 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
591 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
592 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
593 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599
600
601 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
604 I40E_PTT_UNUSED_ENTRY(25),
605 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
606 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
607 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
608
609
610 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
611 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
612 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
613 I40E_PTT_UNUSED_ENTRY(32),
614 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
615 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
616 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
617
618
619 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
620 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
621 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
622 I40E_PTT_UNUSED_ENTRY(39),
623 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
624 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
625 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
626
627
628 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
629
630
631 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
632 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
633 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
634 I40E_PTT_UNUSED_ENTRY(47),
635 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
636 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
637 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
638
639
640 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
641 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
642 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
643 I40E_PTT_UNUSED_ENTRY(54),
644 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
645 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
646 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
647
648
649 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
650
651
652 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
653 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
654 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
655 I40E_PTT_UNUSED_ENTRY(62),
656 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
657 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
658 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
659
660
661 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
662 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
663 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
664 I40E_PTT_UNUSED_ENTRY(69),
665 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
666 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
667 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
668
669
670 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
671
672
673 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
674 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
675 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
676 I40E_PTT_UNUSED_ENTRY(77),
677 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
678 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
679 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
680
681
682 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
683 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
684 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
685 I40E_PTT_UNUSED_ENTRY(84),
686 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
687 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
688 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
689
690
691 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
692 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
693 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
694 I40E_PTT_UNUSED_ENTRY(91),
695 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
696 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
697 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
698
699
700 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
701 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
702 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
703 I40E_PTT_UNUSED_ENTRY(98),
704 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
705 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
706 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
707
708
709 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
710 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
711 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
712 I40E_PTT_UNUSED_ENTRY(105),
713 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
714 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
715 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
716
717
718 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
719
720
721 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
722 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
723 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
724 I40E_PTT_UNUSED_ENTRY(113),
725 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
726 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
727 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
728
729
730 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
731 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
732 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
733 I40E_PTT_UNUSED_ENTRY(120),
734 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
735 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
736 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
737
738
739 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
740
741
742 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
743 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
744 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
745 I40E_PTT_UNUSED_ENTRY(128),
746 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
747 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
748 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
749
750
751 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
752 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
753 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
754 I40E_PTT_UNUSED_ENTRY(135),
755 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
756 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
757 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
758
759
760 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
761
762
763 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
764 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
765 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
766 I40E_PTT_UNUSED_ENTRY(143),
767 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
768 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
769 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
770
771
772 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
773 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
774 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
775 I40E_PTT_UNUSED_ENTRY(150),
776 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
777 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
778 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
779
780
781 I40E_PTT_UNUSED_ENTRY(154),
782 I40E_PTT_UNUSED_ENTRY(155),
783 I40E_PTT_UNUSED_ENTRY(156),
784 I40E_PTT_UNUSED_ENTRY(157),
785 I40E_PTT_UNUSED_ENTRY(158),
786 I40E_PTT_UNUSED_ENTRY(159),
787
788 I40E_PTT_UNUSED_ENTRY(160),
789 I40E_PTT_UNUSED_ENTRY(161),
790 I40E_PTT_UNUSED_ENTRY(162),
791 I40E_PTT_UNUSED_ENTRY(163),
792 I40E_PTT_UNUSED_ENTRY(164),
793 I40E_PTT_UNUSED_ENTRY(165),
794 I40E_PTT_UNUSED_ENTRY(166),
795 I40E_PTT_UNUSED_ENTRY(167),
796 I40E_PTT_UNUSED_ENTRY(168),
797 I40E_PTT_UNUSED_ENTRY(169),
798
799 I40E_PTT_UNUSED_ENTRY(170),
800 I40E_PTT_UNUSED_ENTRY(171),
801 I40E_PTT_UNUSED_ENTRY(172),
802 I40E_PTT_UNUSED_ENTRY(173),
803 I40E_PTT_UNUSED_ENTRY(174),
804 I40E_PTT_UNUSED_ENTRY(175),
805 I40E_PTT_UNUSED_ENTRY(176),
806 I40E_PTT_UNUSED_ENTRY(177),
807 I40E_PTT_UNUSED_ENTRY(178),
808 I40E_PTT_UNUSED_ENTRY(179),
809
810 I40E_PTT_UNUSED_ENTRY(180),
811 I40E_PTT_UNUSED_ENTRY(181),
812 I40E_PTT_UNUSED_ENTRY(182),
813 I40E_PTT_UNUSED_ENTRY(183),
814 I40E_PTT_UNUSED_ENTRY(184),
815 I40E_PTT_UNUSED_ENTRY(185),
816 I40E_PTT_UNUSED_ENTRY(186),
817 I40E_PTT_UNUSED_ENTRY(187),
818 I40E_PTT_UNUSED_ENTRY(188),
819 I40E_PTT_UNUSED_ENTRY(189),
820
821 I40E_PTT_UNUSED_ENTRY(190),
822 I40E_PTT_UNUSED_ENTRY(191),
823 I40E_PTT_UNUSED_ENTRY(192),
824 I40E_PTT_UNUSED_ENTRY(193),
825 I40E_PTT_UNUSED_ENTRY(194),
826 I40E_PTT_UNUSED_ENTRY(195),
827 I40E_PTT_UNUSED_ENTRY(196),
828 I40E_PTT_UNUSED_ENTRY(197),
829 I40E_PTT_UNUSED_ENTRY(198),
830 I40E_PTT_UNUSED_ENTRY(199),
831
832 I40E_PTT_UNUSED_ENTRY(200),
833 I40E_PTT_UNUSED_ENTRY(201),
834 I40E_PTT_UNUSED_ENTRY(202),
835 I40E_PTT_UNUSED_ENTRY(203),
836 I40E_PTT_UNUSED_ENTRY(204),
837 I40E_PTT_UNUSED_ENTRY(205),
838 I40E_PTT_UNUSED_ENTRY(206),
839 I40E_PTT_UNUSED_ENTRY(207),
840 I40E_PTT_UNUSED_ENTRY(208),
841 I40E_PTT_UNUSED_ENTRY(209),
842
843 I40E_PTT_UNUSED_ENTRY(210),
844 I40E_PTT_UNUSED_ENTRY(211),
845 I40E_PTT_UNUSED_ENTRY(212),
846 I40E_PTT_UNUSED_ENTRY(213),
847 I40E_PTT_UNUSED_ENTRY(214),
848 I40E_PTT_UNUSED_ENTRY(215),
849 I40E_PTT_UNUSED_ENTRY(216),
850 I40E_PTT_UNUSED_ENTRY(217),
851 I40E_PTT_UNUSED_ENTRY(218),
852 I40E_PTT_UNUSED_ENTRY(219),
853
854 I40E_PTT_UNUSED_ENTRY(220),
855 I40E_PTT_UNUSED_ENTRY(221),
856 I40E_PTT_UNUSED_ENTRY(222),
857 I40E_PTT_UNUSED_ENTRY(223),
858 I40E_PTT_UNUSED_ENTRY(224),
859 I40E_PTT_UNUSED_ENTRY(225),
860 I40E_PTT_UNUSED_ENTRY(226),
861 I40E_PTT_UNUSED_ENTRY(227),
862 I40E_PTT_UNUSED_ENTRY(228),
863 I40E_PTT_UNUSED_ENTRY(229),
864
865 I40E_PTT_UNUSED_ENTRY(230),
866 I40E_PTT_UNUSED_ENTRY(231),
867 I40E_PTT_UNUSED_ENTRY(232),
868 I40E_PTT_UNUSED_ENTRY(233),
869 I40E_PTT_UNUSED_ENTRY(234),
870 I40E_PTT_UNUSED_ENTRY(235),
871 I40E_PTT_UNUSED_ENTRY(236),
872 I40E_PTT_UNUSED_ENTRY(237),
873 I40E_PTT_UNUSED_ENTRY(238),
874 I40E_PTT_UNUSED_ENTRY(239),
875
876 I40E_PTT_UNUSED_ENTRY(240),
877 I40E_PTT_UNUSED_ENTRY(241),
878 I40E_PTT_UNUSED_ENTRY(242),
879 I40E_PTT_UNUSED_ENTRY(243),
880 I40E_PTT_UNUSED_ENTRY(244),
881 I40E_PTT_UNUSED_ENTRY(245),
882 I40E_PTT_UNUSED_ENTRY(246),
883 I40E_PTT_UNUSED_ENTRY(247),
884 I40E_PTT_UNUSED_ENTRY(248),
885 I40E_PTT_UNUSED_ENTRY(249),
886
887 I40E_PTT_UNUSED_ENTRY(250),
888 I40E_PTT_UNUSED_ENTRY(251),
889 I40E_PTT_UNUSED_ENTRY(252),
890 I40E_PTT_UNUSED_ENTRY(253),
891 I40E_PTT_UNUSED_ENTRY(254),
892 I40E_PTT_UNUSED_ENTRY(255)
893 };
894
895
896
897
898
899
900
901
902
903
904
905
906
907 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
908 {
909 i40e_status status = 0;
910 u32 port, ari, func_rid;
911
912 i40e_set_mac_type(hw);
913
914 switch (hw->mac.type) {
915 case I40E_MAC_XL710:
916 case I40E_MAC_X722:
917 break;
918 default:
919 return I40E_ERR_DEVICE_NOT_SUPPORTED;
920 }
921
922 hw->phy.get_link_info = true;
923
924
925 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
926 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
927 hw->port = (u8)port;
928 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
929 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
930 func_rid = rd32(hw, I40E_PF_FUNC_RID);
931 if (ari)
932 hw->pf_id = (u8)(func_rid & 0xff);
933 else
934 hw->pf_id = (u8)(func_rid & 0x7);
935
936 if (hw->mac.type == I40E_MAC_X722)
937 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
938 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
939
940 status = i40e_init_nvm(hw);
941 return status;
942 }
943
944
945
946
947
948
949
950
951 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
952 u16 *flags,
953 struct i40e_aqc_mac_address_read_data *addrs,
954 struct i40e_asq_cmd_details *cmd_details)
955 {
956 struct i40e_aq_desc desc;
957 struct i40e_aqc_mac_address_read *cmd_data =
958 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
959 i40e_status status;
960
961 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
962 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
963
964 status = i40e_asq_send_command(hw, &desc, addrs,
965 sizeof(*addrs), cmd_details);
966 *flags = le16_to_cpu(cmd_data->command_flags);
967
968 return status;
969 }
970
971
972
973
974
975
976
977
978 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
979 u16 flags, u8 *mac_addr,
980 struct i40e_asq_cmd_details *cmd_details)
981 {
982 struct i40e_aq_desc desc;
983 struct i40e_aqc_mac_address_write *cmd_data =
984 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
985 i40e_status status;
986
987 i40e_fill_default_direct_cmd_desc(&desc,
988 i40e_aqc_opc_mac_address_write);
989 cmd_data->command_flags = cpu_to_le16(flags);
990 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
991 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
992 ((u32)mac_addr[3] << 16) |
993 ((u32)mac_addr[4] << 8) |
994 mac_addr[5]);
995
996 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
997
998 return status;
999 }
1000
1001
1002
1003
1004
1005
1006
1007
1008 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1009 {
1010 struct i40e_aqc_mac_address_read_data addrs;
1011 i40e_status status;
1012 u16 flags = 0;
1013
1014 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1015
1016 if (flags & I40E_AQC_LAN_ADDR_VALID)
1017 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1018
1019 return status;
1020 }
1021
1022
1023
1024
1025
1026
1027
1028
1029 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1030 {
1031 struct i40e_aqc_mac_address_read_data addrs;
1032 i40e_status status;
1033 u16 flags = 0;
1034
1035 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1036 if (status)
1037 return status;
1038
1039 if (flags & I40E_AQC_PORT_ADDR_VALID)
1040 ether_addr_copy(mac_addr, addrs.port_mac);
1041 else
1042 status = I40E_ERR_INVALID_MAC_ADDR;
1043
1044 return status;
1045 }
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1057 {
1058 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1059 u32 reg_block = 0;
1060 u32 reg_val;
1061
1062 if (abs_queue_idx >= 128) {
1063 reg_block = abs_queue_idx / 128;
1064 abs_queue_idx %= 128;
1065 }
1066
1067 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1068 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1069 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1070
1071 if (enable)
1072 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1073 else
1074 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1075
1076 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1077 }
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1088 u32 pba_num_size)
1089 {
1090 i40e_status status = 0;
1091 u16 pba_word = 0;
1092 u16 pba_size = 0;
1093 u16 pba_ptr = 0;
1094 u16 i = 0;
1095
1096 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1097 if (status || (pba_word != 0xFAFA)) {
1098 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1099 return status;
1100 }
1101
1102 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1103 if (status) {
1104 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1105 return status;
1106 }
1107
1108 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1109 if (status) {
1110 hw_dbg(hw, "Failed to read PBA Block size.\n");
1111 return status;
1112 }
1113
1114
1115
1116
1117 pba_size--;
1118 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1119 hw_dbg(hw, "Buffer to small for PBA data.\n");
1120 return I40E_ERR_PARAM;
1121 }
1122
1123 for (i = 0; i < pba_size; i++) {
1124 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1125 if (status) {
1126 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1127 return status;
1128 }
1129
1130 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1131 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1132 }
1133 pba_num[(pba_size * 2)] = '\0';
1134
1135 return status;
1136 }
1137
1138
1139
1140
1141
1142 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1143 {
1144 enum i40e_media_type media;
1145
1146 switch (hw->phy.link_info.phy_type) {
1147 case I40E_PHY_TYPE_10GBASE_SR:
1148 case I40E_PHY_TYPE_10GBASE_LR:
1149 case I40E_PHY_TYPE_1000BASE_SX:
1150 case I40E_PHY_TYPE_1000BASE_LX:
1151 case I40E_PHY_TYPE_40GBASE_SR4:
1152 case I40E_PHY_TYPE_40GBASE_LR4:
1153 case I40E_PHY_TYPE_25GBASE_LR:
1154 case I40E_PHY_TYPE_25GBASE_SR:
1155 media = I40E_MEDIA_TYPE_FIBER;
1156 break;
1157 case I40E_PHY_TYPE_100BASE_TX:
1158 case I40E_PHY_TYPE_1000BASE_T:
1159 case I40E_PHY_TYPE_2_5GBASE_T:
1160 case I40E_PHY_TYPE_5GBASE_T:
1161 case I40E_PHY_TYPE_10GBASE_T:
1162 media = I40E_MEDIA_TYPE_BASET;
1163 break;
1164 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1165 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1166 case I40E_PHY_TYPE_10GBASE_CR1:
1167 case I40E_PHY_TYPE_40GBASE_CR4:
1168 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1169 case I40E_PHY_TYPE_40GBASE_AOC:
1170 case I40E_PHY_TYPE_10GBASE_AOC:
1171 case I40E_PHY_TYPE_25GBASE_CR:
1172 case I40E_PHY_TYPE_25GBASE_AOC:
1173 case I40E_PHY_TYPE_25GBASE_ACC:
1174 media = I40E_MEDIA_TYPE_DA;
1175 break;
1176 case I40E_PHY_TYPE_1000BASE_KX:
1177 case I40E_PHY_TYPE_10GBASE_KX4:
1178 case I40E_PHY_TYPE_10GBASE_KR:
1179 case I40E_PHY_TYPE_40GBASE_KR4:
1180 case I40E_PHY_TYPE_20GBASE_KR2:
1181 case I40E_PHY_TYPE_25GBASE_KR:
1182 media = I40E_MEDIA_TYPE_BACKPLANE;
1183 break;
1184 case I40E_PHY_TYPE_SGMII:
1185 case I40E_PHY_TYPE_XAUI:
1186 case I40E_PHY_TYPE_XFI:
1187 case I40E_PHY_TYPE_XLAUI:
1188 case I40E_PHY_TYPE_XLPPI:
1189 default:
1190 media = I40E_MEDIA_TYPE_UNKNOWN;
1191 break;
1192 }
1193
1194 return media;
1195 }
1196
1197
1198
1199
1200
1201
1202 static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1203 u32 retry_limit)
1204 {
1205 u32 cnt, reg = 0;
1206
1207 for (cnt = 0; cnt < retry_limit; cnt++) {
1208 reg = rd32(hw, I40E_GLGEN_RSTAT);
1209 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1210 return 0;
1211 msleep(100);
1212 }
1213
1214 hw_dbg(hw, "Global reset failed.\n");
1215 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1216
1217 return I40E_ERR_RESET_FAILED;
1218 }
1219
1220 #define I40E_PF_RESET_WAIT_COUNT_A0 200
1221 #define I40E_PF_RESET_WAIT_COUNT 200
1222
1223
1224
1225
1226
1227
1228
1229 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1230 {
1231 u32 cnt = 0;
1232 u32 cnt1 = 0;
1233 u32 reg = 0;
1234 u32 grst_del;
1235
1236
1237
1238
1239
1240 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1241 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1242 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1243
1244
1245
1246
1247 grst_del = grst_del * 20;
1248
1249 for (cnt = 0; cnt < grst_del; cnt++) {
1250 reg = rd32(hw, I40E_GLGEN_RSTAT);
1251 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1252 break;
1253 msleep(100);
1254 }
1255 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1256 hw_dbg(hw, "Global reset polling failed to complete.\n");
1257 return I40E_ERR_RESET_FAILED;
1258 }
1259
1260
1261 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1262 reg = rd32(hw, I40E_GLNVM_ULD);
1263 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1264 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1265 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1266 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1267 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1268 break;
1269 }
1270 usleep_range(10000, 20000);
1271 }
1272 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1273 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1274 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1275 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1276 return I40E_ERR_RESET_FAILED;
1277 }
1278
1279
1280
1281
1282 if (!cnt) {
1283 u32 reg2 = 0;
1284 if (hw->revision_id == 0)
1285 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1286 else
1287 cnt = I40E_PF_RESET_WAIT_COUNT;
1288 reg = rd32(hw, I40E_PFGEN_CTRL);
1289 wr32(hw, I40E_PFGEN_CTRL,
1290 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1291 for (; cnt; cnt--) {
1292 reg = rd32(hw, I40E_PFGEN_CTRL);
1293 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1294 break;
1295 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1296 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1297 break;
1298 usleep_range(1000, 2000);
1299 }
1300 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1301 if (i40e_poll_globr(hw, grst_del))
1302 return I40E_ERR_RESET_FAILED;
1303 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1304 hw_dbg(hw, "PF reset polling failed to complete.\n");
1305 return I40E_ERR_RESET_FAILED;
1306 }
1307 }
1308
1309 i40e_clear_pxe_mode(hw);
1310
1311 return 0;
1312 }
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322 void i40e_clear_hw(struct i40e_hw *hw)
1323 {
1324 u32 num_queues, base_queue;
1325 u32 num_pf_int;
1326 u32 num_vf_int;
1327 u32 num_vfs;
1328 u32 i, j;
1329 u32 val;
1330 u32 eol = 0x7ff;
1331
1332
1333 val = rd32(hw, I40E_GLPCI_CNF2);
1334 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1335 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1336 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1337 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1338
1339 val = rd32(hw, I40E_PFLAN_QALLOC);
1340 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1341 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1342 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1343 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1344 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1345 num_queues = (j - base_queue) + 1;
1346 else
1347 num_queues = 0;
1348
1349 val = rd32(hw, I40E_PF_VT_PFALLOC);
1350 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1351 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1352 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1353 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1354 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1355 num_vfs = (j - i) + 1;
1356 else
1357 num_vfs = 0;
1358
1359
1360 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1361 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1362 for (i = 0; i < num_pf_int - 2; i++)
1363 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1364
1365
1366 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1367 wr32(hw, I40E_PFINT_LNKLST0, val);
1368 for (i = 0; i < num_pf_int - 2; i++)
1369 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1370 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1371 for (i = 0; i < num_vfs; i++)
1372 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1373 for (i = 0; i < num_vf_int - 2; i++)
1374 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1375
1376
1377 for (i = 0; i < num_queues; i++) {
1378 u32 abs_queue_idx = base_queue + i;
1379 u32 reg_block = 0;
1380
1381 if (abs_queue_idx >= 128) {
1382 reg_block = abs_queue_idx / 128;
1383 abs_queue_idx %= 128;
1384 }
1385
1386 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1387 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1388 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1389 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1390
1391 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1392 }
1393 udelay(400);
1394
1395
1396 for (i = 0; i < num_queues; i++) {
1397 wr32(hw, I40E_QINT_TQCTL(i), 0);
1398 wr32(hw, I40E_QTX_ENA(i), 0);
1399 wr32(hw, I40E_QINT_RQCTL(i), 0);
1400 wr32(hw, I40E_QRX_ENA(i), 0);
1401 }
1402
1403
1404 udelay(50);
1405 }
1406
1407
1408
1409
1410
1411
1412
1413
1414 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1415 {
1416 u32 reg;
1417
1418 if (i40e_check_asq_alive(hw))
1419 i40e_aq_clear_pxe_mode(hw, NULL);
1420
1421
1422 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1423
1424 if (hw->revision_id == 0) {
1425
1426 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1427 } else {
1428 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1429 }
1430 }
1431
1432
1433
1434
1435
1436
1437
1438
1439 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1440 {
1441 u32 gpio_val = 0;
1442 u32 port;
1443
1444 if (!hw->func_caps.led[idx])
1445 return 0;
1446
1447 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1448 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1449 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1450
1451
1452
1453
1454 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1455 (port != hw->port))
1456 return 0;
1457
1458 return gpio_val;
1459 }
1460
1461 #define I40E_COMBINED_ACTIVITY 0xA
1462 #define I40E_FILTER_ACTIVITY 0xE
1463 #define I40E_LINK_ACTIVITY 0xC
1464 #define I40E_MAC_ACTIVITY 0xD
1465 #define I40E_LED0 22
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476 u32 i40e_led_get(struct i40e_hw *hw)
1477 {
1478 u32 mode = 0;
1479 int i;
1480
1481
1482
1483
1484 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1485 u32 gpio_val = i40e_led_is_mine(hw, i);
1486
1487 if (!gpio_val)
1488 continue;
1489
1490 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1491 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1492 break;
1493 }
1494
1495 return mode;
1496 }
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1508 {
1509 int i;
1510
1511 if (mode & 0xfffffff0)
1512 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1513
1514
1515
1516
1517 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1518 u32 gpio_val = i40e_led_is_mine(hw, i);
1519
1520 if (!gpio_val)
1521 continue;
1522 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1523
1524 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1525 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1526
1527 if (blink)
1528 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1529 else
1530 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1531
1532 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1533 break;
1534 }
1535 }
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1550 bool qualified_modules, bool report_init,
1551 struct i40e_aq_get_phy_abilities_resp *abilities,
1552 struct i40e_asq_cmd_details *cmd_details)
1553 {
1554 struct i40e_aq_desc desc;
1555 i40e_status status;
1556 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1557 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1558
1559 if (!abilities)
1560 return I40E_ERR_PARAM;
1561
1562 do {
1563 i40e_fill_default_direct_cmd_desc(&desc,
1564 i40e_aqc_opc_get_phy_abilities);
1565
1566 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1567 if (abilities_size > I40E_AQ_LARGE_BUF)
1568 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1569
1570 if (qualified_modules)
1571 desc.params.external.param0 |=
1572 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1573
1574 if (report_init)
1575 desc.params.external.param0 |=
1576 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1577
1578 status = i40e_asq_send_command(hw, &desc, abilities,
1579 abilities_size, cmd_details);
1580
1581 switch (hw->aq.asq_last_status) {
1582 case I40E_AQ_RC_EIO:
1583 status = I40E_ERR_UNKNOWN_PHY;
1584 break;
1585 case I40E_AQ_RC_EAGAIN:
1586 usleep_range(1000, 2000);
1587 total_delay++;
1588 status = I40E_ERR_TIMEOUT;
1589 break;
1590
1591 default:
1592 break;
1593 }
1594
1595 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1596 (total_delay < max_delay));
1597
1598 if (status)
1599 return status;
1600
1601 if (report_init) {
1602 if (hw->mac.type == I40E_MAC_XL710 &&
1603 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1604 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1605 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1606 } else {
1607 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1608 hw->phy.phy_types |=
1609 ((u64)abilities->phy_type_ext << 32);
1610 }
1611 }
1612
1613 return status;
1614 }
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1629 struct i40e_aq_set_phy_config *config,
1630 struct i40e_asq_cmd_details *cmd_details)
1631 {
1632 struct i40e_aq_desc desc;
1633 struct i40e_aq_set_phy_config *cmd =
1634 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1635 enum i40e_status_code status;
1636
1637 if (!config)
1638 return I40E_ERR_PARAM;
1639
1640 i40e_fill_default_direct_cmd_desc(&desc,
1641 i40e_aqc_opc_set_phy_config);
1642
1643 *cmd = *config;
1644
1645 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1646
1647 return status;
1648 }
1649
1650 static noinline_for_stack enum i40e_status_code
1651 i40e_set_fc_status(struct i40e_hw *hw,
1652 struct i40e_aq_get_phy_abilities_resp *abilities,
1653 bool atomic_restart)
1654 {
1655 struct i40e_aq_set_phy_config config;
1656 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1657 u8 pause_mask = 0x0;
1658
1659 switch (fc_mode) {
1660 case I40E_FC_FULL:
1661 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1662 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1663 break;
1664 case I40E_FC_RX_PAUSE:
1665 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1666 break;
1667 case I40E_FC_TX_PAUSE:
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1669 break;
1670 default:
1671 break;
1672 }
1673
1674 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1675
1676 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1677 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1678
1679 config.abilities |= pause_mask;
1680
1681 if (config.abilities == abilities->abilities)
1682 return 0;
1683
1684
1685 if (atomic_restart)
1686 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1687
1688 config.phy_type = abilities->phy_type;
1689 config.phy_type_ext = abilities->phy_type_ext;
1690 config.link_speed = abilities->link_speed;
1691 config.eee_capability = abilities->eee_capability;
1692 config.eeer = abilities->eeer_val;
1693 config.low_power_ctrl = abilities->d3_lpan;
1694 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1695 I40E_AQ_PHY_FEC_CONFIG_MASK;
1696
1697 return i40e_aq_set_phy_config(hw, &config, NULL);
1698 }
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1709 bool atomic_restart)
1710 {
1711 struct i40e_aq_get_phy_abilities_resp abilities;
1712 enum i40e_status_code status;
1713
1714 *aq_failures = 0x0;
1715
1716
1717 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1718 NULL);
1719 if (status) {
1720 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1721 return status;
1722 }
1723
1724 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1725 if (status)
1726 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1727
1728
1729 status = i40e_update_link_info(hw);
1730 if (status) {
1731
1732
1733
1734
1735 msleep(1000);
1736 status = i40e_update_link_info(hw);
1737 }
1738 if (status)
1739 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1740
1741 return status;
1742 }
1743
1744
1745
1746
1747
1748
1749
1750
1751 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1752 struct i40e_asq_cmd_details *cmd_details)
1753 {
1754 i40e_status status;
1755 struct i40e_aq_desc desc;
1756 struct i40e_aqc_clear_pxe *cmd =
1757 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1758
1759 i40e_fill_default_direct_cmd_desc(&desc,
1760 i40e_aqc_opc_clear_pxe_mode);
1761
1762 cmd->rx_cnt = 0x2;
1763
1764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1765
1766 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1767
1768 return status;
1769 }
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1780 bool enable_link,
1781 struct i40e_asq_cmd_details *cmd_details)
1782 {
1783 struct i40e_aq_desc desc;
1784 struct i40e_aqc_set_link_restart_an *cmd =
1785 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1786 i40e_status status;
1787
1788 i40e_fill_default_direct_cmd_desc(&desc,
1789 i40e_aqc_opc_set_link_restart_an);
1790
1791 cmd->command = I40E_AQ_PHY_RESTART_AN;
1792 if (enable_link)
1793 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1794 else
1795 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1796
1797 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1798
1799 return status;
1800 }
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1812 bool enable_lse, struct i40e_link_status *link,
1813 struct i40e_asq_cmd_details *cmd_details)
1814 {
1815 struct i40e_aq_desc desc;
1816 struct i40e_aqc_get_link_status *resp =
1817 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1818 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1819 i40e_status status;
1820 bool tx_pause, rx_pause;
1821 u16 command_flags;
1822
1823 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1824
1825 if (enable_lse)
1826 command_flags = I40E_AQ_LSE_ENABLE;
1827 else
1828 command_flags = I40E_AQ_LSE_DISABLE;
1829 resp->command_flags = cpu_to_le16(command_flags);
1830
1831 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1832
1833 if (status)
1834 goto aq_get_link_info_exit;
1835
1836
1837 hw->phy.link_info_old = *hw_link_info;
1838
1839
1840 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1841 hw->phy.media_type = i40e_get_media_type(hw);
1842 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1843 hw_link_info->link_info = resp->link_info;
1844 hw_link_info->an_info = resp->an_info;
1845 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1846 I40E_AQ_CONFIG_FEC_RS_ENA);
1847 hw_link_info->ext_info = resp->ext_info;
1848 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1849 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1850 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1851
1852
1853 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1854 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1855 if (tx_pause & rx_pause)
1856 hw->fc.current_mode = I40E_FC_FULL;
1857 else if (tx_pause)
1858 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1859 else if (rx_pause)
1860 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1861 else
1862 hw->fc.current_mode = I40E_FC_NONE;
1863
1864 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1865 hw_link_info->crc_enable = true;
1866 else
1867 hw_link_info->crc_enable = false;
1868
1869 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1870 hw_link_info->lse_enable = true;
1871 else
1872 hw_link_info->lse_enable = false;
1873
1874 if ((hw->mac.type == I40E_MAC_XL710) &&
1875 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1876 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1877 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1878
1879 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
1880 hw->mac.type != I40E_MAC_X722) {
1881 __le32 tmp;
1882
1883 memcpy(&tmp, resp->link_type, sizeof(tmp));
1884 hw->phy.phy_types = le32_to_cpu(tmp);
1885 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1886 }
1887
1888
1889 if (link)
1890 *link = *hw_link_info;
1891
1892
1893 hw->phy.get_link_info = false;
1894
1895 aq_get_link_info_exit:
1896 return status;
1897 }
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1908 u16 mask,
1909 struct i40e_asq_cmd_details *cmd_details)
1910 {
1911 struct i40e_aq_desc desc;
1912 struct i40e_aqc_set_phy_int_mask *cmd =
1913 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1914 i40e_status status;
1915
1916 i40e_fill_default_direct_cmd_desc(&desc,
1917 i40e_aqc_opc_set_phy_int_mask);
1918
1919 cmd->event_mask = cpu_to_le16(mask);
1920
1921 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1922
1923 return status;
1924 }
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1935 struct i40e_asq_cmd_details *cmd_details)
1936 {
1937 struct i40e_aq_desc desc;
1938 struct i40e_aqc_set_phy_debug *cmd =
1939 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1940 i40e_status status;
1941
1942 i40e_fill_default_direct_cmd_desc(&desc,
1943 i40e_aqc_opc_set_phy_debug);
1944
1945 cmd->command_flags = cmd_flags;
1946
1947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1948
1949 return status;
1950 }
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1961 struct i40e_vsi_context *vsi_ctx,
1962 struct i40e_asq_cmd_details *cmd_details)
1963 {
1964 struct i40e_aq_desc desc;
1965 struct i40e_aqc_add_get_update_vsi *cmd =
1966 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1967 struct i40e_aqc_add_get_update_vsi_completion *resp =
1968 (struct i40e_aqc_add_get_update_vsi_completion *)
1969 &desc.params.raw;
1970 i40e_status status;
1971
1972 i40e_fill_default_direct_cmd_desc(&desc,
1973 i40e_aqc_opc_add_vsi);
1974
1975 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1976 cmd->connection_type = vsi_ctx->connection_type;
1977 cmd->vf_id = vsi_ctx->vf_num;
1978 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1979
1980 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1981
1982 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1983 sizeof(vsi_ctx->info), cmd_details);
1984
1985 if (status)
1986 goto aq_add_vsi_exit;
1987
1988 vsi_ctx->seid = le16_to_cpu(resp->seid);
1989 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1990 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1991 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1992
1993 aq_add_vsi_exit:
1994 return status;
1995 }
1996
1997
1998
1999
2000
2001
2002
2003 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
2004 u16 seid,
2005 struct i40e_asq_cmd_details *cmd_details)
2006 {
2007 struct i40e_aq_desc desc;
2008 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2009 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2010 &desc.params.raw;
2011 i40e_status status;
2012
2013 i40e_fill_default_direct_cmd_desc(&desc,
2014 i40e_aqc_opc_set_vsi_promiscuous_modes);
2015
2016 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2017 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2018 cmd->seid = cpu_to_le16(seid);
2019
2020 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2021
2022 return status;
2023 }
2024
2025
2026
2027
2028
2029
2030
2031 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2032 u16 seid,
2033 struct i40e_asq_cmd_details *cmd_details)
2034 {
2035 struct i40e_aq_desc desc;
2036 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2037 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2038 &desc.params.raw;
2039 i40e_status status;
2040
2041 i40e_fill_default_direct_cmd_desc(&desc,
2042 i40e_aqc_opc_set_vsi_promiscuous_modes);
2043
2044 cmd->promiscuous_flags = cpu_to_le16(0);
2045 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2046 cmd->seid = cpu_to_le16(seid);
2047
2048 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2049
2050 return status;
2051 }
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2062 u16 seid, bool set,
2063 struct i40e_asq_cmd_details *cmd_details,
2064 bool rx_only_promisc)
2065 {
2066 struct i40e_aq_desc desc;
2067 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2068 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2069 i40e_status status;
2070 u16 flags = 0;
2071
2072 i40e_fill_default_direct_cmd_desc(&desc,
2073 i40e_aqc_opc_set_vsi_promiscuous_modes);
2074
2075 if (set) {
2076 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2077 if (rx_only_promisc &&
2078 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2079 (hw->aq.api_maj_ver > 1)))
2080 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2081 }
2082
2083 cmd->promiscuous_flags = cpu_to_le16(flags);
2084
2085 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2086 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2087 (hw->aq.api_maj_ver > 1))
2088 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2089
2090 cmd->seid = cpu_to_le16(seid);
2091 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2092
2093 return status;
2094 }
2095
2096
2097
2098
2099
2100
2101
2102
2103 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2104 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2105 {
2106 struct i40e_aq_desc desc;
2107 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2108 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2109 i40e_status status;
2110 u16 flags = 0;
2111
2112 i40e_fill_default_direct_cmd_desc(&desc,
2113 i40e_aqc_opc_set_vsi_promiscuous_modes);
2114
2115 if (set)
2116 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2117
2118 cmd->promiscuous_flags = cpu_to_le16(flags);
2119
2120 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2121
2122 cmd->seid = cpu_to_le16(seid);
2123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2124
2125 return status;
2126 }
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2137 u16 seid, bool enable,
2138 u16 vid,
2139 struct i40e_asq_cmd_details *cmd_details)
2140 {
2141 struct i40e_aq_desc desc;
2142 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2143 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2144 enum i40e_status_code status;
2145 u16 flags = 0;
2146
2147 i40e_fill_default_direct_cmd_desc(&desc,
2148 i40e_aqc_opc_set_vsi_promiscuous_modes);
2149
2150 if (enable)
2151 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2152
2153 cmd->promiscuous_flags = cpu_to_le16(flags);
2154 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2155 cmd->seid = cpu_to_le16(seid);
2156 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2157
2158 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2159
2160 return status;
2161 }
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2172 u16 seid, bool enable,
2173 u16 vid,
2174 struct i40e_asq_cmd_details *cmd_details)
2175 {
2176 struct i40e_aq_desc desc;
2177 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2178 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2179 enum i40e_status_code status;
2180 u16 flags = 0;
2181
2182 i40e_fill_default_direct_cmd_desc(&desc,
2183 i40e_aqc_opc_set_vsi_promiscuous_modes);
2184
2185 if (enable)
2186 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2187
2188 cmd->promiscuous_flags = cpu_to_le16(flags);
2189 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2190 cmd->seid = cpu_to_le16(seid);
2191 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2192
2193 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2194
2195 return status;
2196 }
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2207 u16 seid, bool enable, u16 vid,
2208 struct i40e_asq_cmd_details *cmd_details)
2209 {
2210 struct i40e_aq_desc desc;
2211 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2212 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2213 i40e_status status;
2214 u16 flags = 0;
2215
2216 i40e_fill_default_direct_cmd_desc(&desc,
2217 i40e_aqc_opc_set_vsi_promiscuous_modes);
2218
2219 if (enable)
2220 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2221
2222 cmd->promiscuous_flags = cpu_to_le16(flags);
2223 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2224 cmd->seid = cpu_to_le16(seid);
2225 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2226
2227 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2228
2229 return status;
2230 }
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2242 u16 seid, bool set_filter,
2243 struct i40e_asq_cmd_details *cmd_details)
2244 {
2245 struct i40e_aq_desc desc;
2246 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2247 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2248 i40e_status status;
2249
2250 i40e_fill_default_direct_cmd_desc(&desc,
2251 i40e_aqc_opc_set_vsi_promiscuous_modes);
2252
2253 if (set_filter)
2254 cmd->promiscuous_flags
2255 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2256 else
2257 cmd->promiscuous_flags
2258 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2259
2260 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2261 cmd->seid = cpu_to_le16(seid);
2262 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2263
2264 return status;
2265 }
2266
2267
2268
2269
2270
2271
2272
2273
2274 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2275 u16 seid, bool enable,
2276 struct i40e_asq_cmd_details *cmd_details)
2277 {
2278 struct i40e_aq_desc desc;
2279 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2280 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2281 i40e_status status;
2282 u16 flags = 0;
2283
2284 i40e_fill_default_direct_cmd_desc(&desc,
2285 i40e_aqc_opc_set_vsi_promiscuous_modes);
2286 if (enable)
2287 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2288
2289 cmd->promiscuous_flags = cpu_to_le16(flags);
2290 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2291 cmd->seid = cpu_to_le16(seid);
2292
2293 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2294
2295 return status;
2296 }
2297
2298
2299
2300
2301
2302
2303
2304 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2305 struct i40e_vsi_context *vsi_ctx,
2306 struct i40e_asq_cmd_details *cmd_details)
2307 {
2308 struct i40e_aq_desc desc;
2309 struct i40e_aqc_add_get_update_vsi *cmd =
2310 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2311 struct i40e_aqc_add_get_update_vsi_completion *resp =
2312 (struct i40e_aqc_add_get_update_vsi_completion *)
2313 &desc.params.raw;
2314 i40e_status status;
2315
2316 i40e_fill_default_direct_cmd_desc(&desc,
2317 i40e_aqc_opc_get_vsi_parameters);
2318
2319 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2320
2321 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2322
2323 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2324 sizeof(vsi_ctx->info), NULL);
2325
2326 if (status)
2327 goto aq_get_vsi_params_exit;
2328
2329 vsi_ctx->seid = le16_to_cpu(resp->seid);
2330 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2331 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2332 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2333
2334 aq_get_vsi_params_exit:
2335 return status;
2336 }
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2347 struct i40e_vsi_context *vsi_ctx,
2348 struct i40e_asq_cmd_details *cmd_details)
2349 {
2350 struct i40e_aq_desc desc;
2351 struct i40e_aqc_add_get_update_vsi *cmd =
2352 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2353 struct i40e_aqc_add_get_update_vsi_completion *resp =
2354 (struct i40e_aqc_add_get_update_vsi_completion *)
2355 &desc.params.raw;
2356 i40e_status status;
2357
2358 i40e_fill_default_direct_cmd_desc(&desc,
2359 i40e_aqc_opc_update_vsi_parameters);
2360 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2361
2362 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2363
2364 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2365 sizeof(vsi_ctx->info), cmd_details);
2366
2367 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2368 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2369
2370 return status;
2371 }
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2384 struct i40e_aqc_get_switch_config_resp *buf,
2385 u16 buf_size, u16 *start_seid,
2386 struct i40e_asq_cmd_details *cmd_details)
2387 {
2388 struct i40e_aq_desc desc;
2389 struct i40e_aqc_switch_seid *scfg =
2390 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2391 i40e_status status;
2392
2393 i40e_fill_default_direct_cmd_desc(&desc,
2394 i40e_aqc_opc_get_switch_config);
2395 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2396 if (buf_size > I40E_AQ_LARGE_BUF)
2397 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2398 scfg->seid = cpu_to_le16(*start_seid);
2399
2400 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2401 *start_seid = le16_to_cpu(scfg->seid);
2402
2403 return status;
2404 }
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2418 u16 flags,
2419 u16 valid_flags, u8 mode,
2420 struct i40e_asq_cmd_details *cmd_details)
2421 {
2422 struct i40e_aq_desc desc;
2423 struct i40e_aqc_set_switch_config *scfg =
2424 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2425 enum i40e_status_code status;
2426
2427 i40e_fill_default_direct_cmd_desc(&desc,
2428 i40e_aqc_opc_set_switch_config);
2429 scfg->flags = cpu_to_le16(flags);
2430 scfg->valid_flags = cpu_to_le16(valid_flags);
2431 scfg->mode = mode;
2432 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2433 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2434 scfg->first_tag = cpu_to_le16(hw->first_tag);
2435 scfg->second_tag = cpu_to_le16(hw->second_tag);
2436 }
2437 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2438
2439 return status;
2440 }
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2455 u16 *fw_major_version, u16 *fw_minor_version,
2456 u32 *fw_build,
2457 u16 *api_major_version, u16 *api_minor_version,
2458 struct i40e_asq_cmd_details *cmd_details)
2459 {
2460 struct i40e_aq_desc desc;
2461 struct i40e_aqc_get_version *resp =
2462 (struct i40e_aqc_get_version *)&desc.params.raw;
2463 i40e_status status;
2464
2465 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2466
2467 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2468
2469 if (!status) {
2470 if (fw_major_version)
2471 *fw_major_version = le16_to_cpu(resp->fw_major);
2472 if (fw_minor_version)
2473 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2474 if (fw_build)
2475 *fw_build = le32_to_cpu(resp->fw_build);
2476 if (api_major_version)
2477 *api_major_version = le16_to_cpu(resp->api_major);
2478 if (api_minor_version)
2479 *api_minor_version = le16_to_cpu(resp->api_minor);
2480 }
2481
2482 return status;
2483 }
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2494 struct i40e_driver_version *dv,
2495 struct i40e_asq_cmd_details *cmd_details)
2496 {
2497 struct i40e_aq_desc desc;
2498 struct i40e_aqc_driver_version *cmd =
2499 (struct i40e_aqc_driver_version *)&desc.params.raw;
2500 i40e_status status;
2501 u16 len;
2502
2503 if (dv == NULL)
2504 return I40E_ERR_PARAM;
2505
2506 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2507
2508 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2509 cmd->driver_major_ver = dv->major_version;
2510 cmd->driver_minor_ver = dv->minor_version;
2511 cmd->driver_build_ver = dv->build_version;
2512 cmd->driver_subbuild_ver = dv->subbuild_version;
2513
2514 len = 0;
2515 while (len < sizeof(dv->driver_string) &&
2516 (dv->driver_string[len] < 0x80) &&
2517 dv->driver_string[len])
2518 len++;
2519 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2520 len, cmd_details);
2521
2522 return status;
2523 }
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2536 {
2537 i40e_status status = 0;
2538
2539 if (hw->phy.get_link_info) {
2540 status = i40e_update_link_info(hw);
2541
2542 if (status)
2543 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2544 status);
2545 }
2546
2547 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2548
2549 return status;
2550 }
2551
2552
2553
2554
2555
2556 noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
2557 {
2558 struct i40e_aq_get_phy_abilities_resp abilities;
2559 i40e_status status = 0;
2560
2561 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2562 if (status)
2563 return status;
2564
2565
2566 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2567 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2568 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2569 status = i40e_aq_get_phy_capabilities(hw, false, false,
2570 &abilities, NULL);
2571 if (status)
2572 return status;
2573
2574 if (abilities.fec_cfg_curr_mod_ext_info &
2575 I40E_AQ_ENABLE_FEC_AUTO)
2576 hw->phy.link_info.req_fec_info =
2577 (I40E_AQ_REQUEST_FEC_KR |
2578 I40E_AQ_REQUEST_FEC_RS);
2579 else
2580 hw->phy.link_info.req_fec_info =
2581 abilities.fec_cfg_curr_mod_ext_info &
2582 (I40E_AQ_REQUEST_FEC_KR |
2583 I40E_AQ_REQUEST_FEC_RS);
2584
2585 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2586 sizeof(hw->phy.link_info.module_type));
2587 }
2588
2589 return status;
2590 }
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2607 u16 downlink_seid, u8 enabled_tc,
2608 bool default_port, u16 *veb_seid,
2609 bool enable_stats,
2610 struct i40e_asq_cmd_details *cmd_details)
2611 {
2612 struct i40e_aq_desc desc;
2613 struct i40e_aqc_add_veb *cmd =
2614 (struct i40e_aqc_add_veb *)&desc.params.raw;
2615 struct i40e_aqc_add_veb_completion *resp =
2616 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2617 i40e_status status;
2618 u16 veb_flags = 0;
2619
2620
2621 if (!!uplink_seid != !!downlink_seid)
2622 return I40E_ERR_PARAM;
2623
2624 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2625
2626 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2627 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2628 cmd->enable_tcs = enabled_tc;
2629 if (!uplink_seid)
2630 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2631 if (default_port)
2632 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2633 else
2634 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2635
2636
2637 if (!enable_stats)
2638 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2639
2640 cmd->veb_flags = cpu_to_le16(veb_flags);
2641
2642 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2643
2644 if (!status && veb_seid)
2645 *veb_seid = le16_to_cpu(resp->veb_seid);
2646
2647 return status;
2648 }
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2665 u16 veb_seid, u16 *switch_id,
2666 bool *floating, u16 *statistic_index,
2667 u16 *vebs_used, u16 *vebs_free,
2668 struct i40e_asq_cmd_details *cmd_details)
2669 {
2670 struct i40e_aq_desc desc;
2671 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2672 (struct i40e_aqc_get_veb_parameters_completion *)
2673 &desc.params.raw;
2674 i40e_status status;
2675
2676 if (veb_seid == 0)
2677 return I40E_ERR_PARAM;
2678
2679 i40e_fill_default_direct_cmd_desc(&desc,
2680 i40e_aqc_opc_get_veb_parameters);
2681 cmd_resp->seid = cpu_to_le16(veb_seid);
2682
2683 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2684 if (status)
2685 goto get_veb_exit;
2686
2687 if (switch_id)
2688 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2689 if (statistic_index)
2690 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2691 if (vebs_used)
2692 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2693 if (vebs_free)
2694 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2695 if (floating) {
2696 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2697
2698 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2699 *floating = true;
2700 else
2701 *floating = false;
2702 }
2703
2704 get_veb_exit:
2705 return status;
2706 }
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2719 struct i40e_aqc_add_macvlan_element_data *mv_list,
2720 u16 count, struct i40e_asq_cmd_details *cmd_details)
2721 {
2722 struct i40e_aq_desc desc;
2723 struct i40e_aqc_macvlan *cmd =
2724 (struct i40e_aqc_macvlan *)&desc.params.raw;
2725 i40e_status status;
2726 u16 buf_size;
2727 int i;
2728
2729 if (count == 0 || !mv_list || !hw)
2730 return I40E_ERR_PARAM;
2731
2732 buf_size = count * sizeof(*mv_list);
2733
2734
2735 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2736 cmd->num_addresses = cpu_to_le16(count);
2737 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2738 cmd->seid[1] = 0;
2739 cmd->seid[2] = 0;
2740
2741 for (i = 0; i < count; i++)
2742 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2743 mv_list[i].flags |=
2744 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2745
2746 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2747 if (buf_size > I40E_AQ_LARGE_BUF)
2748 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2749
2750 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2751 cmd_details);
2752
2753 return status;
2754 }
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2767 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2768 u16 count, struct i40e_asq_cmd_details *cmd_details)
2769 {
2770 struct i40e_aq_desc desc;
2771 struct i40e_aqc_macvlan *cmd =
2772 (struct i40e_aqc_macvlan *)&desc.params.raw;
2773 i40e_status status;
2774 u16 buf_size;
2775
2776 if (count == 0 || !mv_list || !hw)
2777 return I40E_ERR_PARAM;
2778
2779 buf_size = count * sizeof(*mv_list);
2780
2781
2782 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2783 cmd->num_addresses = cpu_to_le16(count);
2784 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2785 cmd->seid[1] = 0;
2786 cmd->seid[2] = 0;
2787
2788 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2789 if (buf_size > I40E_AQ_LARGE_BUF)
2790 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2791
2792 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2793 cmd_details);
2794
2795 return status;
2796 }
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2816 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2817 u16 count, __le16 *mr_list,
2818 struct i40e_asq_cmd_details *cmd_details,
2819 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2820 {
2821 struct i40e_aq_desc desc;
2822 struct i40e_aqc_add_delete_mirror_rule *cmd =
2823 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2824 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2825 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2826 i40e_status status;
2827 u16 buf_size;
2828
2829 buf_size = count * sizeof(*mr_list);
2830
2831
2832 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2833 cmd->seid = cpu_to_le16(sw_seid);
2834 cmd->rule_type = cpu_to_le16(rule_type &
2835 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2836 cmd->num_entries = cpu_to_le16(count);
2837
2838 cmd->destination = cpu_to_le16(id);
2839 if (mr_list) {
2840 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2841 I40E_AQ_FLAG_RD));
2842 if (buf_size > I40E_AQ_LARGE_BUF)
2843 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2844 }
2845
2846 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2847 cmd_details);
2848 if (!status ||
2849 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2850 if (rule_id)
2851 *rule_id = le16_to_cpu(resp->rule_id);
2852 if (rules_used)
2853 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2854 if (rules_free)
2855 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2856 }
2857 return status;
2858 }
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2876 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2877 struct i40e_asq_cmd_details *cmd_details,
2878 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2879 {
2880 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2881 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2882 if (count == 0 || !mr_list)
2883 return I40E_ERR_PARAM;
2884 }
2885
2886 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2887 rule_type, dest_vsi, count, mr_list,
2888 cmd_details, rule_id, rules_used, rules_free);
2889 }
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2907 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2908 struct i40e_asq_cmd_details *cmd_details,
2909 u16 *rules_used, u16 *rules_free)
2910 {
2911
2912 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2913
2914
2915
2916
2917 if (count == 0 || !mr_list)
2918 return I40E_ERR_PARAM;
2919 }
2920
2921 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2922 rule_type, rule_id, count, mr_list,
2923 cmd_details, NULL, rules_used, rules_free);
2924 }
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2939 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2940 struct i40e_asq_cmd_details *cmd_details)
2941 {
2942 struct i40e_aq_desc desc;
2943 struct i40e_aqc_pf_vf_message *cmd =
2944 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2945 i40e_status status;
2946
2947 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2948 cmd->id = cpu_to_le32(vfid);
2949 desc.cookie_high = cpu_to_le32(v_opcode);
2950 desc.cookie_low = cpu_to_le32(v_retval);
2951 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2952 if (msglen) {
2953 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2954 I40E_AQ_FLAG_RD));
2955 if (msglen > I40E_AQ_LARGE_BUF)
2956 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2957 desc.datalen = cpu_to_le16(msglen);
2958 }
2959 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2960
2961 return status;
2962 }
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2974 u32 reg_addr, u64 *reg_val,
2975 struct i40e_asq_cmd_details *cmd_details)
2976 {
2977 struct i40e_aq_desc desc;
2978 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2979 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2980 i40e_status status;
2981
2982 if (reg_val == NULL)
2983 return I40E_ERR_PARAM;
2984
2985 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2986
2987 cmd_resp->address = cpu_to_le32(reg_addr);
2988
2989 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2990
2991 if (!status) {
2992 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2993 (u64)le32_to_cpu(cmd_resp->value_low);
2994 }
2995
2996 return status;
2997 }
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
3009 u32 reg_addr, u64 reg_val,
3010 struct i40e_asq_cmd_details *cmd_details)
3011 {
3012 struct i40e_aq_desc desc;
3013 struct i40e_aqc_debug_reg_read_write *cmd =
3014 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3015 i40e_status status;
3016
3017 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3018
3019 cmd->address = cpu_to_le32(reg_addr);
3020 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
3021 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
3022
3023 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3024
3025 return status;
3026 }
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
3040 enum i40e_aq_resources_ids resource,
3041 enum i40e_aq_resource_access_type access,
3042 u8 sdp_number, u64 *timeout,
3043 struct i40e_asq_cmd_details *cmd_details)
3044 {
3045 struct i40e_aq_desc desc;
3046 struct i40e_aqc_request_resource *cmd_resp =
3047 (struct i40e_aqc_request_resource *)&desc.params.raw;
3048 i40e_status status;
3049
3050 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3051
3052 cmd_resp->resource_id = cpu_to_le16(resource);
3053 cmd_resp->access_type = cpu_to_le16(access);
3054 cmd_resp->resource_number = cpu_to_le32(sdp_number);
3055
3056 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3057
3058
3059
3060
3061
3062
3063 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3064 *timeout = le32_to_cpu(cmd_resp->timeout);
3065
3066 return status;
3067 }
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3079 enum i40e_aq_resources_ids resource,
3080 u8 sdp_number,
3081 struct i40e_asq_cmd_details *cmd_details)
3082 {
3083 struct i40e_aq_desc desc;
3084 struct i40e_aqc_request_resource *cmd =
3085 (struct i40e_aqc_request_resource *)&desc.params.raw;
3086 i40e_status status;
3087
3088 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3089
3090 cmd->resource_id = cpu_to_le16(resource);
3091 cmd->resource_number = cpu_to_le32(sdp_number);
3092
3093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3094
3095 return status;
3096 }
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3111 u32 offset, u16 length, void *data,
3112 bool last_command,
3113 struct i40e_asq_cmd_details *cmd_details)
3114 {
3115 struct i40e_aq_desc desc;
3116 struct i40e_aqc_nvm_update *cmd =
3117 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3118 i40e_status status;
3119
3120
3121 if (offset & 0xFF000000) {
3122 status = I40E_ERR_PARAM;
3123 goto i40e_aq_read_nvm_exit;
3124 }
3125
3126 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3127
3128
3129 if (last_command)
3130 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3131 cmd->module_pointer = module_pointer;
3132 cmd->offset = cpu_to_le32(offset);
3133 cmd->length = cpu_to_le16(length);
3134
3135 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3136 if (length > I40E_AQ_LARGE_BUF)
3137 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3138
3139 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3140
3141 i40e_aq_read_nvm_exit:
3142 return status;
3143 }
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3157 u32 offset, u16 length, bool last_command,
3158 struct i40e_asq_cmd_details *cmd_details)
3159 {
3160 struct i40e_aq_desc desc;
3161 struct i40e_aqc_nvm_update *cmd =
3162 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3163 i40e_status status;
3164
3165
3166 if (offset & 0xFF000000) {
3167 status = I40E_ERR_PARAM;
3168 goto i40e_aq_erase_nvm_exit;
3169 }
3170
3171 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3172
3173
3174 if (last_command)
3175 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3176 cmd->module_pointer = module_pointer;
3177 cmd->offset = cpu_to_le32(offset);
3178 cmd->length = cpu_to_le16(length);
3179
3180 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3181
3182 i40e_aq_erase_nvm_exit:
3183 return status;
3184 }
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3196 u32 cap_count,
3197 enum i40e_admin_queue_opc list_type_opc)
3198 {
3199 struct i40e_aqc_list_capabilities_element_resp *cap;
3200 u32 valid_functions, num_functions;
3201 u32 number, logical_id, phys_id;
3202 struct i40e_hw_capabilities *p;
3203 u16 id, ocp_cfg_word0;
3204 i40e_status status;
3205 u8 major_rev;
3206 u32 i = 0;
3207
3208 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3209
3210 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3211 p = &hw->dev_caps;
3212 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3213 p = &hw->func_caps;
3214 else
3215 return;
3216
3217 for (i = 0; i < cap_count; i++, cap++) {
3218 id = le16_to_cpu(cap->id);
3219 number = le32_to_cpu(cap->number);
3220 logical_id = le32_to_cpu(cap->logical_id);
3221 phys_id = le32_to_cpu(cap->phys_id);
3222 major_rev = cap->major_rev;
3223
3224 switch (id) {
3225 case I40E_AQ_CAP_ID_SWITCH_MODE:
3226 p->switch_mode = number;
3227 break;
3228 case I40E_AQ_CAP_ID_MNG_MODE:
3229 p->management_mode = number;
3230 if (major_rev > 1) {
3231 p->mng_protocols_over_mctp = logical_id;
3232 i40e_debug(hw, I40E_DEBUG_INIT,
3233 "HW Capability: Protocols over MCTP = %d\n",
3234 p->mng_protocols_over_mctp);
3235 } else {
3236 p->mng_protocols_over_mctp = 0;
3237 }
3238 break;
3239 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3240 p->npar_enable = number;
3241 break;
3242 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3243 p->os2bmc = number;
3244 break;
3245 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3246 p->valid_functions = number;
3247 break;
3248 case I40E_AQ_CAP_ID_SRIOV:
3249 if (number == 1)
3250 p->sr_iov_1_1 = true;
3251 break;
3252 case I40E_AQ_CAP_ID_VF:
3253 p->num_vfs = number;
3254 p->vf_base_id = logical_id;
3255 break;
3256 case I40E_AQ_CAP_ID_VMDQ:
3257 if (number == 1)
3258 p->vmdq = true;
3259 break;
3260 case I40E_AQ_CAP_ID_8021QBG:
3261 if (number == 1)
3262 p->evb_802_1_qbg = true;
3263 break;
3264 case I40E_AQ_CAP_ID_8021QBR:
3265 if (number == 1)
3266 p->evb_802_1_qbh = true;
3267 break;
3268 case I40E_AQ_CAP_ID_VSI:
3269 p->num_vsis = number;
3270 break;
3271 case I40E_AQ_CAP_ID_DCB:
3272 if (number == 1) {
3273 p->dcb = true;
3274 p->enabled_tcmap = logical_id;
3275 p->maxtc = phys_id;
3276 }
3277 break;
3278 case I40E_AQ_CAP_ID_FCOE:
3279 if (number == 1)
3280 p->fcoe = true;
3281 break;
3282 case I40E_AQ_CAP_ID_ISCSI:
3283 if (number == 1)
3284 p->iscsi = true;
3285 break;
3286 case I40E_AQ_CAP_ID_RSS:
3287 p->rss = true;
3288 p->rss_table_size = number;
3289 p->rss_table_entry_width = logical_id;
3290 break;
3291 case I40E_AQ_CAP_ID_RXQ:
3292 p->num_rx_qp = number;
3293 p->base_queue = phys_id;
3294 break;
3295 case I40E_AQ_CAP_ID_TXQ:
3296 p->num_tx_qp = number;
3297 p->base_queue = phys_id;
3298 break;
3299 case I40E_AQ_CAP_ID_MSIX:
3300 p->num_msix_vectors = number;
3301 i40e_debug(hw, I40E_DEBUG_INIT,
3302 "HW Capability: MSIX vector count = %d\n",
3303 p->num_msix_vectors);
3304 break;
3305 case I40E_AQ_CAP_ID_VF_MSIX:
3306 p->num_msix_vectors_vf = number;
3307 break;
3308 case I40E_AQ_CAP_ID_FLEX10:
3309 if (major_rev == 1) {
3310 if (number == 1) {
3311 p->flex10_enable = true;
3312 p->flex10_capable = true;
3313 }
3314 } else {
3315
3316 if (number & 1)
3317 p->flex10_enable = true;
3318 if (number & 2)
3319 p->flex10_capable = true;
3320 }
3321 p->flex10_mode = logical_id;
3322 p->flex10_status = phys_id;
3323 break;
3324 case I40E_AQ_CAP_ID_CEM:
3325 if (number == 1)
3326 p->mgmt_cem = true;
3327 break;
3328 case I40E_AQ_CAP_ID_IWARP:
3329 if (number == 1)
3330 p->iwarp = true;
3331 break;
3332 case I40E_AQ_CAP_ID_LED:
3333 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3334 p->led[phys_id] = true;
3335 break;
3336 case I40E_AQ_CAP_ID_SDP:
3337 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3338 p->sdp[phys_id] = true;
3339 break;
3340 case I40E_AQ_CAP_ID_MDIO:
3341 if (number == 1) {
3342 p->mdio_port_num = phys_id;
3343 p->mdio_port_mode = logical_id;
3344 }
3345 break;
3346 case I40E_AQ_CAP_ID_1588:
3347 if (number == 1)
3348 p->ieee_1588 = true;
3349 break;
3350 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3351 p->fd = true;
3352 p->fd_filters_guaranteed = number;
3353 p->fd_filters_best_effort = logical_id;
3354 break;
3355 case I40E_AQ_CAP_ID_WSR_PROT:
3356 p->wr_csr_prot = (u64)number;
3357 p->wr_csr_prot |= (u64)logical_id << 32;
3358 break;
3359 case I40E_AQ_CAP_ID_NVM_MGMT:
3360 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3361 p->sec_rev_disabled = true;
3362 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3363 p->update_disabled = true;
3364 break;
3365 default:
3366 break;
3367 }
3368 }
3369
3370 if (p->fcoe)
3371 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3372
3373
3374
3375
3376 if (p->npar_enable || p->flex10_enable)
3377 p->fcoe = false;
3378
3379
3380 hw->num_ports = 0;
3381 for (i = 0; i < 4; i++) {
3382 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3383 u64 port_cfg = 0;
3384
3385
3386
3387
3388 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3389 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3390 hw->num_ports++;
3391 }
3392
3393
3394
3395
3396
3397
3398
3399
3400 if (hw->mac.type == I40E_MAC_X722) {
3401 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3402 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3403 2 * I40E_SR_OCP_CFG_WORD0,
3404 sizeof(ocp_cfg_word0),
3405 &ocp_cfg_word0, true, NULL);
3406 if (!status &&
3407 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3408 hw->num_ports = 4;
3409 i40e_release_nvm(hw);
3410 }
3411 }
3412
3413 valid_functions = p->valid_functions;
3414 num_functions = 0;
3415 while (valid_functions) {
3416 if (valid_functions & 1)
3417 num_functions++;
3418 valid_functions >>= 1;
3419 }
3420
3421
3422
3423
3424 if (hw->num_ports != 0) {
3425 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3426 hw->num_partitions = num_functions / hw->num_ports;
3427 }
3428
3429
3430
3431
3432 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3433 }
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3447 void *buff, u16 buff_size, u16 *data_size,
3448 enum i40e_admin_queue_opc list_type_opc,
3449 struct i40e_asq_cmd_details *cmd_details)
3450 {
3451 struct i40e_aqc_list_capabilites *cmd;
3452 struct i40e_aq_desc desc;
3453 i40e_status status = 0;
3454
3455 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3456
3457 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3458 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3459 status = I40E_ERR_PARAM;
3460 goto exit;
3461 }
3462
3463 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3464
3465 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3466 if (buff_size > I40E_AQ_LARGE_BUF)
3467 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3468
3469 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3470 *data_size = le16_to_cpu(desc.datalen);
3471
3472 if (status)
3473 goto exit;
3474
3475 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3476 list_type_opc);
3477
3478 exit:
3479 return status;
3480 }
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3496 u32 offset, u16 length, void *data,
3497 bool last_command, u8 preservation_flags,
3498 struct i40e_asq_cmd_details *cmd_details)
3499 {
3500 struct i40e_aq_desc desc;
3501 struct i40e_aqc_nvm_update *cmd =
3502 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3503 i40e_status status;
3504
3505
3506 if (offset & 0xFF000000) {
3507 status = I40E_ERR_PARAM;
3508 goto i40e_aq_update_nvm_exit;
3509 }
3510
3511 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3512
3513
3514 if (last_command)
3515 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3516 if (hw->mac.type == I40E_MAC_X722) {
3517 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3518 cmd->command_flags |=
3519 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3520 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3521 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3522 cmd->command_flags |=
3523 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3524 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3525 }
3526 cmd->module_pointer = module_pointer;
3527 cmd->offset = cpu_to_le32(offset);
3528 cmd->length = cpu_to_le16(length);
3529
3530 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3531 if (length > I40E_AQ_LARGE_BUF)
3532 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3533
3534 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3535
3536 i40e_aq_update_nvm_exit:
3537 return status;
3538 }
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3549 u8 rearrange_nvm,
3550 struct i40e_asq_cmd_details *cmd_details)
3551 {
3552 struct i40e_aqc_nvm_update *cmd;
3553 i40e_status status;
3554 struct i40e_aq_desc desc;
3555
3556 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3557
3558 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3559
3560 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3561 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3562
3563 if (!rearrange_nvm) {
3564 status = I40E_ERR_PARAM;
3565 goto i40e_aq_rearrange_nvm_exit;
3566 }
3567
3568 cmd->command_flags |= rearrange_nvm;
3569 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3570
3571 i40e_aq_rearrange_nvm_exit:
3572 return status;
3573 }
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3589 u8 mib_type, void *buff, u16 buff_size,
3590 u16 *local_len, u16 *remote_len,
3591 struct i40e_asq_cmd_details *cmd_details)
3592 {
3593 struct i40e_aq_desc desc;
3594 struct i40e_aqc_lldp_get_mib *cmd =
3595 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3596 struct i40e_aqc_lldp_get_mib *resp =
3597 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3598 i40e_status status;
3599
3600 if (buff_size == 0 || !buff)
3601 return I40E_ERR_PARAM;
3602
3603 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3604
3605 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3606
3607 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3608 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3609 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3610
3611 desc.datalen = cpu_to_le16(buff_size);
3612
3613 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3614 if (buff_size > I40E_AQ_LARGE_BUF)
3615 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3616
3617 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3618 if (!status) {
3619 if (local_len != NULL)
3620 *local_len = le16_to_cpu(resp->local_len);
3621 if (remote_len != NULL)
3622 *remote_len = le16_to_cpu(resp->remote_len);
3623 }
3624
3625 return status;
3626 }
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3638 bool enable_update,
3639 struct i40e_asq_cmd_details *cmd_details)
3640 {
3641 struct i40e_aq_desc desc;
3642 struct i40e_aqc_lldp_update_mib *cmd =
3643 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3644 i40e_status status;
3645
3646 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3647
3648 if (!enable_update)
3649 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3650
3651 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3652
3653 return status;
3654 }
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666 enum i40e_status_code
3667 i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3668 struct i40e_asq_cmd_details *cmd_details)
3669 {
3670 struct i40e_aq_desc desc;
3671 struct i40e_aqc_lldp_restore *cmd =
3672 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3673 i40e_status status;
3674
3675 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
3676 i40e_debug(hw, I40E_DEBUG_ALL,
3677 "Restore LLDP not supported by current FW version.\n");
3678 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3679 }
3680
3681 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3682
3683 if (restore)
3684 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3685
3686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3687
3688 if (setting)
3689 *setting = cmd->command & 1;
3690
3691 return status;
3692 }
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3704 bool persist,
3705 struct i40e_asq_cmd_details *cmd_details)
3706 {
3707 struct i40e_aq_desc desc;
3708 struct i40e_aqc_lldp_stop *cmd =
3709 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3710 i40e_status status;
3711
3712 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3713
3714 if (shutdown_agent)
3715 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3716
3717 if (persist) {
3718 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3719 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3720 else
3721 i40e_debug(hw, I40E_DEBUG_ALL,
3722 "Persistent Stop LLDP not supported by current FW version.\n");
3723 }
3724
3725 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3726
3727 return status;
3728 }
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3741 struct i40e_asq_cmd_details *cmd_details)
3742 {
3743 struct i40e_aq_desc desc;
3744 struct i40e_aqc_lldp_start *cmd =
3745 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3746 i40e_status status;
3747
3748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3749
3750 cmd->command = I40E_AQ_LLDP_AGENT_START;
3751
3752 if (persist) {
3753 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3754 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3755 else
3756 i40e_debug(hw, I40E_DEBUG_ALL,
3757 "Persistent Start LLDP not supported by current FW version.\n");
3758 }
3759
3760 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3761
3762 return status;
3763 }
3764
3765
3766
3767
3768
3769
3770
3771
3772 enum i40e_status_code
3773 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3774 struct i40e_asq_cmd_details *cmd_details)
3775 {
3776 struct i40e_aq_desc desc;
3777 struct i40e_aqc_set_dcb_parameters *cmd =
3778 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3779 i40e_status status;
3780
3781 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
3782 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3783
3784 i40e_fill_default_direct_cmd_desc(&desc,
3785 i40e_aqc_opc_set_dcb_parameters);
3786
3787 if (dcb_enable) {
3788 cmd->valid_flags = I40E_DCB_VALID;
3789 cmd->command = I40E_AQ_DCB_SET_AGENT;
3790 }
3791 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3792
3793 return status;
3794 }
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3806 void *buff, u16 buff_size,
3807 struct i40e_asq_cmd_details *cmd_details)
3808 {
3809 struct i40e_aq_desc desc;
3810 i40e_status status;
3811
3812 if (buff_size == 0 || !buff)
3813 return I40E_ERR_PARAM;
3814
3815 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3816
3817 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3818 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3819 cmd_details);
3820
3821 return status;
3822 }
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3837 u16 udp_port, u8 protocol_index,
3838 u8 *filter_index,
3839 struct i40e_asq_cmd_details *cmd_details)
3840 {
3841 struct i40e_aq_desc desc;
3842 struct i40e_aqc_add_udp_tunnel *cmd =
3843 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3844 struct i40e_aqc_del_udp_tunnel_completion *resp =
3845 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3846 i40e_status status;
3847
3848 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3849
3850 cmd->udp_port = cpu_to_le16(udp_port);
3851 cmd->protocol_type = protocol_index;
3852
3853 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3854
3855 if (!status && filter_index)
3856 *filter_index = resp->index;
3857
3858 return status;
3859 }
3860
3861
3862
3863
3864
3865
3866
3867 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3868 struct i40e_asq_cmd_details *cmd_details)
3869 {
3870 struct i40e_aq_desc desc;
3871 struct i40e_aqc_remove_udp_tunnel *cmd =
3872 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3873 i40e_status status;
3874
3875 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3876
3877 cmd->index = index;
3878
3879 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3880
3881 return status;
3882 }
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3893 struct i40e_asq_cmd_details *cmd_details)
3894 {
3895 struct i40e_aq_desc desc;
3896 struct i40e_aqc_switch_seid *cmd =
3897 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3898 i40e_status status;
3899
3900 if (seid == 0)
3901 return I40E_ERR_PARAM;
3902
3903 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3904
3905 cmd->seid = cpu_to_le16(seid);
3906
3907 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3908
3909 return status;
3910 }
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3922 struct i40e_asq_cmd_details *cmd_details)
3923 {
3924 struct i40e_aq_desc desc;
3925 i40e_status status;
3926
3927 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3928
3929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3930
3931 return status;
3932 }
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3946 void *buff, u16 buff_size,
3947 enum i40e_admin_queue_opc opcode,
3948 struct i40e_asq_cmd_details *cmd_details)
3949 {
3950 struct i40e_aq_desc desc;
3951 struct i40e_aqc_tx_sched_ind *cmd =
3952 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3953 i40e_status status;
3954 bool cmd_param_flag = false;
3955
3956 switch (opcode) {
3957 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3958 case i40e_aqc_opc_configure_vsi_tc_bw:
3959 case i40e_aqc_opc_enable_switching_comp_ets:
3960 case i40e_aqc_opc_modify_switching_comp_ets:
3961 case i40e_aqc_opc_disable_switching_comp_ets:
3962 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3963 case i40e_aqc_opc_configure_switching_comp_bw_config:
3964 cmd_param_flag = true;
3965 break;
3966 case i40e_aqc_opc_query_vsi_bw_config:
3967 case i40e_aqc_opc_query_vsi_ets_sla_config:
3968 case i40e_aqc_opc_query_switching_comp_ets_config:
3969 case i40e_aqc_opc_query_port_ets_config:
3970 case i40e_aqc_opc_query_switching_comp_bw_config:
3971 cmd_param_flag = false;
3972 break;
3973 default:
3974 return I40E_ERR_PARAM;
3975 }
3976
3977 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3978
3979
3980 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3981 if (cmd_param_flag)
3982 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3983 if (buff_size > I40E_AQ_LARGE_BUF)
3984 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3985
3986 desc.datalen = cpu_to_le16(buff_size);
3987
3988 cmd->vsi_seid = cpu_to_le16(seid);
3989
3990 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3991
3992 return status;
3993 }
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4004 u16 seid, u16 credit, u8 max_credit,
4005 struct i40e_asq_cmd_details *cmd_details)
4006 {
4007 struct i40e_aq_desc desc;
4008 struct i40e_aqc_configure_vsi_bw_limit *cmd =
4009 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4010 i40e_status status;
4011
4012 i40e_fill_default_direct_cmd_desc(&desc,
4013 i40e_aqc_opc_configure_vsi_bw_limit);
4014
4015 cmd->vsi_seid = cpu_to_le16(seid);
4016 cmd->credit = cpu_to_le16(credit);
4017 cmd->max_credit = max_credit;
4018
4019 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4020
4021 return status;
4022 }
4023
4024
4025
4026
4027
4028
4029
4030
4031 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4032 u16 seid,
4033 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4034 struct i40e_asq_cmd_details *cmd_details)
4035 {
4036 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4037 i40e_aqc_opc_configure_vsi_tc_bw,
4038 cmd_details);
4039 }
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4050 u16 seid,
4051 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4052 enum i40e_admin_queue_opc opcode,
4053 struct i40e_asq_cmd_details *cmd_details)
4054 {
4055 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4056 sizeof(*ets_data), opcode, cmd_details);
4057 }
4058
4059
4060
4061
4062
4063
4064
4065
4066 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4067 u16 seid,
4068 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4069 struct i40e_asq_cmd_details *cmd_details)
4070 {
4071 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4072 i40e_aqc_opc_configure_switching_comp_bw_config,
4073 cmd_details);
4074 }
4075
4076
4077
4078
4079
4080
4081
4082
4083 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4084 u16 seid,
4085 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4086 struct i40e_asq_cmd_details *cmd_details)
4087 {
4088 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4089 i40e_aqc_opc_query_vsi_bw_config,
4090 cmd_details);
4091 }
4092
4093
4094
4095
4096
4097
4098
4099
4100 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4101 u16 seid,
4102 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4103 struct i40e_asq_cmd_details *cmd_details)
4104 {
4105 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4106 i40e_aqc_opc_query_vsi_ets_sla_config,
4107 cmd_details);
4108 }
4109
4110
4111
4112
4113
4114
4115
4116
4117 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4118 u16 seid,
4119 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4120 struct i40e_asq_cmd_details *cmd_details)
4121 {
4122 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4123 i40e_aqc_opc_query_switching_comp_ets_config,
4124 cmd_details);
4125 }
4126
4127
4128
4129
4130
4131
4132
4133
4134 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4135 u16 seid,
4136 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4137 struct i40e_asq_cmd_details *cmd_details)
4138 {
4139 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4140 i40e_aqc_opc_query_port_ets_config,
4141 cmd_details);
4142 }
4143
4144
4145
4146
4147
4148
4149
4150
4151 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4152 u16 seid,
4153 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4154 struct i40e_asq_cmd_details *cmd_details)
4155 {
4156 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4157 i40e_aqc_opc_query_switching_comp_bw_config,
4158 cmd_details);
4159 }
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4174 struct i40e_filter_control_settings *settings)
4175 {
4176 u32 fcoe_cntx_size, fcoe_filt_size;
4177 u32 pe_cntx_size, pe_filt_size;
4178 u32 fcoe_fmax;
4179 u32 val;
4180
4181
4182 switch (settings->fcoe_filt_num) {
4183 case I40E_HASH_FILTER_SIZE_1K:
4184 case I40E_HASH_FILTER_SIZE_2K:
4185 case I40E_HASH_FILTER_SIZE_4K:
4186 case I40E_HASH_FILTER_SIZE_8K:
4187 case I40E_HASH_FILTER_SIZE_16K:
4188 case I40E_HASH_FILTER_SIZE_32K:
4189 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4190 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4191 break;
4192 default:
4193 return I40E_ERR_PARAM;
4194 }
4195
4196 switch (settings->fcoe_cntx_num) {
4197 case I40E_DMA_CNTX_SIZE_512:
4198 case I40E_DMA_CNTX_SIZE_1K:
4199 case I40E_DMA_CNTX_SIZE_2K:
4200 case I40E_DMA_CNTX_SIZE_4K:
4201 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4202 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4203 break;
4204 default:
4205 return I40E_ERR_PARAM;
4206 }
4207
4208
4209 switch (settings->pe_filt_num) {
4210 case I40E_HASH_FILTER_SIZE_1K:
4211 case I40E_HASH_FILTER_SIZE_2K:
4212 case I40E_HASH_FILTER_SIZE_4K:
4213 case I40E_HASH_FILTER_SIZE_8K:
4214 case I40E_HASH_FILTER_SIZE_16K:
4215 case I40E_HASH_FILTER_SIZE_32K:
4216 case I40E_HASH_FILTER_SIZE_64K:
4217 case I40E_HASH_FILTER_SIZE_128K:
4218 case I40E_HASH_FILTER_SIZE_256K:
4219 case I40E_HASH_FILTER_SIZE_512K:
4220 case I40E_HASH_FILTER_SIZE_1M:
4221 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4222 pe_filt_size <<= (u32)settings->pe_filt_num;
4223 break;
4224 default:
4225 return I40E_ERR_PARAM;
4226 }
4227
4228 switch (settings->pe_cntx_num) {
4229 case I40E_DMA_CNTX_SIZE_512:
4230 case I40E_DMA_CNTX_SIZE_1K:
4231 case I40E_DMA_CNTX_SIZE_2K:
4232 case I40E_DMA_CNTX_SIZE_4K:
4233 case I40E_DMA_CNTX_SIZE_8K:
4234 case I40E_DMA_CNTX_SIZE_16K:
4235 case I40E_DMA_CNTX_SIZE_32K:
4236 case I40E_DMA_CNTX_SIZE_64K:
4237 case I40E_DMA_CNTX_SIZE_128K:
4238 case I40E_DMA_CNTX_SIZE_256K:
4239 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4240 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4241 break;
4242 default:
4243 return I40E_ERR_PARAM;
4244 }
4245
4246
4247 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4248 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4249 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4250 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4251 return I40E_ERR_INVALID_SIZE;
4252
4253 return 0;
4254 }
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4266 struct i40e_filter_control_settings *settings)
4267 {
4268 i40e_status ret = 0;
4269 u32 hash_lut_size = 0;
4270 u32 val;
4271
4272 if (!settings)
4273 return I40E_ERR_PARAM;
4274
4275
4276 ret = i40e_validate_filter_settings(hw, settings);
4277 if (ret)
4278 return ret;
4279
4280
4281 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4282
4283
4284 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4285 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4286 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4287
4288 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4289 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4290 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4291
4292
4293 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4294 val |= ((u32)settings->fcoe_filt_num <<
4295 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4296 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4297
4298 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4299 val |= ((u32)settings->fcoe_cntx_num <<
4300 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4301 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4302
4303
4304 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4305 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4306 hash_lut_size = 1;
4307 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4308 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4309
4310
4311 if (settings->enable_fdir)
4312 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4313 if (settings->enable_ethtype)
4314 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4315 if (settings->enable_macvlan)
4316 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4317
4318 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4319
4320 return 0;
4321 }
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4340 u8 *mac_addr, u16 ethtype, u16 flags,
4341 u16 vsi_seid, u16 queue, bool is_add,
4342 struct i40e_control_filter_stats *stats,
4343 struct i40e_asq_cmd_details *cmd_details)
4344 {
4345 struct i40e_aq_desc desc;
4346 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4347 (struct i40e_aqc_add_remove_control_packet_filter *)
4348 &desc.params.raw;
4349 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4350 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4351 &desc.params.raw;
4352 i40e_status status;
4353
4354 if (vsi_seid == 0)
4355 return I40E_ERR_PARAM;
4356
4357 if (is_add) {
4358 i40e_fill_default_direct_cmd_desc(&desc,
4359 i40e_aqc_opc_add_control_packet_filter);
4360 cmd->queue = cpu_to_le16(queue);
4361 } else {
4362 i40e_fill_default_direct_cmd_desc(&desc,
4363 i40e_aqc_opc_remove_control_packet_filter);
4364 }
4365
4366 if (mac_addr)
4367 ether_addr_copy(cmd->mac, mac_addr);
4368
4369 cmd->etype = cpu_to_le16(ethtype);
4370 cmd->flags = cpu_to_le16(flags);
4371 cmd->seid = cpu_to_le16(vsi_seid);
4372
4373 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4374
4375 if (!status && stats) {
4376 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4377 stats->etype_used = le16_to_cpu(resp->etype_used);
4378 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4379 stats->etype_free = le16_to_cpu(resp->etype_free);
4380 }
4381
4382 return status;
4383 }
4384
4385
4386
4387
4388
4389
4390 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4391 u16 seid)
4392 {
4393 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4394 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4395 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4396 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4397 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4398 i40e_status status;
4399
4400 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4401 seid, 0, true, NULL,
4402 NULL);
4403 if (status)
4404 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4405 }
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4421 u32 reg_addr0, u32 *reg_val0,
4422 u32 reg_addr1, u32 *reg_val1)
4423 {
4424 struct i40e_aq_desc desc;
4425 struct i40e_aqc_alternate_write *cmd_resp =
4426 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4427 i40e_status status;
4428
4429 if (!reg_val0)
4430 return I40E_ERR_PARAM;
4431
4432 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4433 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4434 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4435
4436 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4437
4438 if (!status) {
4439 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4440
4441 if (reg_val1)
4442 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4443 }
4444
4445 return status;
4446 }
4447
4448
4449
4450
4451
4452
4453
4454
4455 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4456 struct i40e_asq_cmd_details *cmd_details)
4457 {
4458 struct i40e_aq_desc desc;
4459 i40e_status status;
4460
4461 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4462
4463 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4464
4465 return status;
4466 }
4467
4468
4469
4470
4471
4472
4473
4474
4475 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4476 {
4477 hw->bus.type = i40e_bus_type_pci_express;
4478
4479 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4480 case PCI_EXP_LNKSTA_NLW_X1:
4481 hw->bus.width = i40e_bus_width_pcie_x1;
4482 break;
4483 case PCI_EXP_LNKSTA_NLW_X2:
4484 hw->bus.width = i40e_bus_width_pcie_x2;
4485 break;
4486 case PCI_EXP_LNKSTA_NLW_X4:
4487 hw->bus.width = i40e_bus_width_pcie_x4;
4488 break;
4489 case PCI_EXP_LNKSTA_NLW_X8:
4490 hw->bus.width = i40e_bus_width_pcie_x8;
4491 break;
4492 default:
4493 hw->bus.width = i40e_bus_width_unknown;
4494 break;
4495 }
4496
4497 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4498 case PCI_EXP_LNKSTA_CLS_2_5GB:
4499 hw->bus.speed = i40e_bus_speed_2500;
4500 break;
4501 case PCI_EXP_LNKSTA_CLS_5_0GB:
4502 hw->bus.speed = i40e_bus_speed_5000;
4503 break;
4504 case PCI_EXP_LNKSTA_CLS_8_0GB:
4505 hw->bus.speed = i40e_bus_speed_8000;
4506 break;
4507 default:
4508 hw->bus.speed = i40e_bus_speed_unknown;
4509 break;
4510 }
4511 }
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4530 u8 table_id, u32 start_index, u16 buff_size,
4531 void *buff, u16 *ret_buff_size,
4532 u8 *ret_next_table, u32 *ret_next_index,
4533 struct i40e_asq_cmd_details *cmd_details)
4534 {
4535 struct i40e_aq_desc desc;
4536 struct i40e_aqc_debug_dump_internals *cmd =
4537 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4538 struct i40e_aqc_debug_dump_internals *resp =
4539 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4540 i40e_status status;
4541
4542 if (buff_size == 0 || !buff)
4543 return I40E_ERR_PARAM;
4544
4545 i40e_fill_default_direct_cmd_desc(&desc,
4546 i40e_aqc_opc_debug_dump_internals);
4547
4548 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4549 if (buff_size > I40E_AQ_LARGE_BUF)
4550 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4551
4552 cmd->cluster_id = cluster_id;
4553 cmd->table_id = table_id;
4554 cmd->idx = cpu_to_le32(start_index);
4555
4556 desc.datalen = cpu_to_le16(buff_size);
4557
4558 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4559 if (!status) {
4560 if (ret_buff_size)
4561 *ret_buff_size = le16_to_cpu(desc.datalen);
4562 if (ret_next_table)
4563 *ret_next_table = resp->table_id;
4564 if (ret_next_index)
4565 *ret_next_index = le32_to_cpu(resp->idx);
4566 }
4567
4568 return status;
4569 }
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4582 u32 *max_bw, u32 *min_bw,
4583 bool *min_valid, bool *max_valid)
4584 {
4585 i40e_status status;
4586 u32 max_bw_addr, min_bw_addr;
4587
4588
4589 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4590 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4591 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4592 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4593 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4594 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4595
4596
4597 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4598 min_bw_addr, min_bw);
4599
4600 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4601 *min_valid = true;
4602 else
4603 *min_valid = false;
4604
4605 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4606 *max_valid = true;
4607 else
4608 *max_valid = false;
4609
4610 return status;
4611 }
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4622 struct i40e_aqc_configure_partition_bw_data *bw_data,
4623 struct i40e_asq_cmd_details *cmd_details)
4624 {
4625 i40e_status status;
4626 struct i40e_aq_desc desc;
4627 u16 bwd_size = sizeof(*bw_data);
4628
4629 i40e_fill_default_direct_cmd_desc(&desc,
4630 i40e_aqc_opc_configure_partition_bw);
4631
4632
4633 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4634 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4635
4636 if (bwd_size > I40E_AQ_LARGE_BUF)
4637 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4638
4639 desc.datalen = cpu_to_le16(bwd_size);
4640
4641 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4642 cmd_details);
4643
4644 return status;
4645 }
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4657 u16 reg, u8 phy_addr, u16 *value)
4658 {
4659 i40e_status status = I40E_ERR_TIMEOUT;
4660 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4661 u32 command = 0;
4662 u16 retry = 1000;
4663
4664 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4665 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4666 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4667 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4668 (I40E_GLGEN_MSCA_MDICMD_MASK);
4669 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4670 do {
4671 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4672 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4673 status = 0;
4674 break;
4675 }
4676 udelay(10);
4677 retry--;
4678 } while (retry);
4679
4680 if (status) {
4681 i40e_debug(hw, I40E_DEBUG_PHY,
4682 "PHY: Can't write command to external PHY.\n");
4683 } else {
4684 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4685 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4686 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4687 }
4688
4689 return status;
4690 }
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4702 u16 reg, u8 phy_addr, u16 value)
4703 {
4704 i40e_status status = I40E_ERR_TIMEOUT;
4705 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4706 u32 command = 0;
4707 u16 retry = 1000;
4708
4709 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4710 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4711
4712 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4713 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4714 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4715 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4716 (I40E_GLGEN_MSCA_MDICMD_MASK);
4717
4718 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4719 do {
4720 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4721 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4722 status = 0;
4723 break;
4724 }
4725 udelay(10);
4726 retry--;
4727 } while (retry);
4728
4729 return status;
4730 }
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4743 u8 page, u16 reg, u8 phy_addr, u16 *value)
4744 {
4745 i40e_status status = I40E_ERR_TIMEOUT;
4746 u32 command = 0;
4747 u16 retry = 1000;
4748 u8 port_num = hw->func_caps.mdio_port_num;
4749
4750 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4751 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4752 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4753 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4754 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4755 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4756 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4757 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4758 do {
4759 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4760 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4761 status = 0;
4762 break;
4763 }
4764 usleep_range(10, 20);
4765 retry--;
4766 } while (retry);
4767
4768 if (status) {
4769 i40e_debug(hw, I40E_DEBUG_PHY,
4770 "PHY: Can't write command to external PHY.\n");
4771 goto phy_read_end;
4772 }
4773
4774 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4775 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4776 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4777 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4778 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4779 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4780 status = I40E_ERR_TIMEOUT;
4781 retry = 1000;
4782 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4783 do {
4784 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4785 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4786 status = 0;
4787 break;
4788 }
4789 usleep_range(10, 20);
4790 retry--;
4791 } while (retry);
4792
4793 if (!status) {
4794 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4795 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4796 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4797 } else {
4798 i40e_debug(hw, I40E_DEBUG_PHY,
4799 "PHY: Can't read register value from external PHY.\n");
4800 }
4801
4802 phy_read_end:
4803 return status;
4804 }
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4817 u8 page, u16 reg, u8 phy_addr, u16 value)
4818 {
4819 i40e_status status = I40E_ERR_TIMEOUT;
4820 u32 command = 0;
4821 u16 retry = 1000;
4822 u8 port_num = hw->func_caps.mdio_port_num;
4823
4824 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4825 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4826 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4827 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4828 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4829 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4830 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4831 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4832 do {
4833 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4834 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4835 status = 0;
4836 break;
4837 }
4838 usleep_range(10, 20);
4839 retry--;
4840 } while (retry);
4841 if (status) {
4842 i40e_debug(hw, I40E_DEBUG_PHY,
4843 "PHY: Can't write command to external PHY.\n");
4844 goto phy_write_end;
4845 }
4846
4847 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4848 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4849
4850 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4851 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4852 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4853 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4854 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4855 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4856 status = I40E_ERR_TIMEOUT;
4857 retry = 1000;
4858 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4859 do {
4860 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4861 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4862 status = 0;
4863 break;
4864 }
4865 usleep_range(10, 20);
4866 retry--;
4867 } while (retry);
4868
4869 phy_write_end:
4870 return status;
4871 }
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4884 u8 page, u16 reg, u8 phy_addr, u16 value)
4885 {
4886 i40e_status status;
4887
4888 switch (hw->device_id) {
4889 case I40E_DEV_ID_1G_BASE_T_X722:
4890 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4891 value);
4892 break;
4893 case I40E_DEV_ID_10G_BASE_T:
4894 case I40E_DEV_ID_10G_BASE_T4:
4895 case I40E_DEV_ID_10G_BASE_T_X722:
4896 case I40E_DEV_ID_25G_B:
4897 case I40E_DEV_ID_25G_SFP28:
4898 status = i40e_write_phy_register_clause45(hw, page, reg,
4899 phy_addr, value);
4900 break;
4901 default:
4902 status = I40E_ERR_UNKNOWN_PHY;
4903 break;
4904 }
4905
4906 return status;
4907 }
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4920 u8 page, u16 reg, u8 phy_addr, u16 *value)
4921 {
4922 i40e_status status;
4923
4924 switch (hw->device_id) {
4925 case I40E_DEV_ID_1G_BASE_T_X722:
4926 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4927 value);
4928 break;
4929 case I40E_DEV_ID_10G_BASE_T:
4930 case I40E_DEV_ID_10G_BASE_T4:
4931 case I40E_DEV_ID_10G_BASE_T_BC:
4932 case I40E_DEV_ID_10G_BASE_T_X722:
4933 case I40E_DEV_ID_25G_B:
4934 case I40E_DEV_ID_25G_SFP28:
4935 status = i40e_read_phy_register_clause45(hw, page, reg,
4936 phy_addr, value);
4937 break;
4938 default:
4939 status = I40E_ERR_UNKNOWN_PHY;
4940 break;
4941 }
4942
4943 return status;
4944 }
4945
4946
4947
4948
4949
4950
4951
4952
4953 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4954 {
4955 u8 port_num = hw->func_caps.mdio_port_num;
4956 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4957
4958 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4959 }
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4970 u32 time, u32 interval)
4971 {
4972 i40e_status status = 0;
4973 u32 i;
4974 u16 led_ctl;
4975 u16 gpio_led_port;
4976 u16 led_reg;
4977 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4978 u8 phy_addr = 0;
4979 u8 port_num;
4980
4981 i = rd32(hw, I40E_PFGEN_PORTNUM);
4982 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4983 phy_addr = i40e_get_phy_address(hw, port_num);
4984
4985 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4986 led_addr++) {
4987 status = i40e_read_phy_register_clause45(hw,
4988 I40E_PHY_COM_REG_PAGE,
4989 led_addr, phy_addr,
4990 &led_reg);
4991 if (status)
4992 goto phy_blinking_end;
4993 led_ctl = led_reg;
4994 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4995 led_reg = 0;
4996 status = i40e_write_phy_register_clause45(hw,
4997 I40E_PHY_COM_REG_PAGE,
4998 led_addr, phy_addr,
4999 led_reg);
5000 if (status)
5001 goto phy_blinking_end;
5002 break;
5003 }
5004 }
5005
5006 if (time > 0 && interval > 0) {
5007 for (i = 0; i < time * 1000; i += interval) {
5008 status = i40e_read_phy_register_clause45(hw,
5009 I40E_PHY_COM_REG_PAGE,
5010 led_addr, phy_addr, &led_reg);
5011 if (status)
5012 goto restore_config;
5013 if (led_reg & I40E_PHY_LED_MANUAL_ON)
5014 led_reg = 0;
5015 else
5016 led_reg = I40E_PHY_LED_MANUAL_ON;
5017 status = i40e_write_phy_register_clause45(hw,
5018 I40E_PHY_COM_REG_PAGE,
5019 led_addr, phy_addr, led_reg);
5020 if (status)
5021 goto restore_config;
5022 msleep(interval);
5023 }
5024 }
5025
5026 restore_config:
5027 status = i40e_write_phy_register_clause45(hw,
5028 I40E_PHY_COM_REG_PAGE,
5029 led_addr, phy_addr, led_ctl);
5030
5031 phy_blinking_end:
5032 return status;
5033 }
5034
5035
5036
5037
5038
5039
5040
5041 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
5042 u32 *reg_val)
5043 {
5044 enum i40e_status_code status;
5045 u8 phy_addr = 0;
5046 u8 port_num;
5047 u32 i;
5048
5049 *reg_val = 0;
5050 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5051 status =
5052 i40e_aq_get_phy_register(hw,
5053 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5054 I40E_PHY_COM_REG_PAGE,
5055 I40E_PHY_LED_PROV_REG_1,
5056 reg_val, NULL);
5057 } else {
5058 i = rd32(hw, I40E_PFGEN_PORTNUM);
5059 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5060 phy_addr = i40e_get_phy_address(hw, port_num);
5061 status = i40e_read_phy_register_clause45(hw,
5062 I40E_PHY_COM_REG_PAGE,
5063 led_addr, phy_addr,
5064 (u16 *)reg_val);
5065 }
5066 return status;
5067 }
5068
5069
5070
5071
5072
5073
5074
5075 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5076 u32 reg_val)
5077 {
5078 enum i40e_status_code status;
5079 u8 phy_addr = 0;
5080 u8 port_num;
5081 u32 i;
5082
5083 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5084 status =
5085 i40e_aq_set_phy_register(hw,
5086 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5087 I40E_PHY_COM_REG_PAGE,
5088 I40E_PHY_LED_PROV_REG_1,
5089 reg_val, NULL);
5090 } else {
5091 i = rd32(hw, I40E_PFGEN_PORTNUM);
5092 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5093 phy_addr = i40e_get_phy_address(hw, port_num);
5094 status = i40e_write_phy_register_clause45(hw,
5095 I40E_PHY_COM_REG_PAGE,
5096 led_addr, phy_addr,
5097 (u16)reg_val);
5098 }
5099
5100 return status;
5101 }
5102
5103
5104
5105
5106
5107
5108
5109
5110 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5111 u16 *val)
5112 {
5113 i40e_status status = 0;
5114 u16 gpio_led_port;
5115 u8 phy_addr = 0;
5116 u16 reg_val;
5117 u16 temp_addr;
5118 u8 port_num;
5119 u32 i;
5120 u32 reg_val_aq;
5121
5122 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5123 status =
5124 i40e_aq_get_phy_register(hw,
5125 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5126 I40E_PHY_COM_REG_PAGE,
5127 I40E_PHY_LED_PROV_REG_1,
5128 ®_val_aq, NULL);
5129 if (status == I40E_SUCCESS)
5130 *val = (u16)reg_val_aq;
5131 return status;
5132 }
5133 temp_addr = I40E_PHY_LED_PROV_REG_1;
5134 i = rd32(hw, I40E_PFGEN_PORTNUM);
5135 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5136 phy_addr = i40e_get_phy_address(hw, port_num);
5137
5138 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5139 temp_addr++) {
5140 status = i40e_read_phy_register_clause45(hw,
5141 I40E_PHY_COM_REG_PAGE,
5142 temp_addr, phy_addr,
5143 ®_val);
5144 if (status)
5145 return status;
5146 *val = reg_val;
5147 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5148 *led_addr = temp_addr;
5149 break;
5150 }
5151 }
5152 return status;
5153 }
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5166 u16 led_addr, u32 mode)
5167 {
5168 i40e_status status = 0;
5169 u32 led_ctl = 0;
5170 u32 led_reg = 0;
5171
5172 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5173 if (status)
5174 return status;
5175 led_ctl = led_reg;
5176 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5177 led_reg = 0;
5178 status = i40e_led_set_reg(hw, led_addr, led_reg);
5179 if (status)
5180 return status;
5181 }
5182 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5183 if (status)
5184 goto restore_config;
5185 if (on)
5186 led_reg = I40E_PHY_LED_MANUAL_ON;
5187 else
5188 led_reg = 0;
5189
5190 status = i40e_led_set_reg(hw, led_addr, led_reg);
5191 if (status)
5192 goto restore_config;
5193 if (mode & I40E_PHY_LED_MODE_ORIG) {
5194 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5195 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5196 }
5197 return status;
5198
5199 restore_config:
5200 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5201 return status;
5202 }
5203
5204
5205
5206
5207
5208
5209
5210
5211
5212
5213
5214 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5215 u32 reg_addr, u32 *reg_val,
5216 struct i40e_asq_cmd_details *cmd_details)
5217 {
5218 struct i40e_aq_desc desc;
5219 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5220 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5221 i40e_status status;
5222
5223 if (!reg_val)
5224 return I40E_ERR_PARAM;
5225
5226 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5227
5228 cmd_resp->address = cpu_to_le32(reg_addr);
5229
5230 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5231
5232 if (status == 0)
5233 *reg_val = le32_to_cpu(cmd_resp->value);
5234
5235 return status;
5236 }
5237
5238
5239
5240
5241
5242
5243 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5244 {
5245 i40e_status status = 0;
5246 bool use_register;
5247 int retry = 5;
5248 u32 val = 0;
5249
5250 use_register = (((hw->aq.api_maj_ver == 1) &&
5251 (hw->aq.api_min_ver < 5)) ||
5252 (hw->mac.type == I40E_MAC_X722));
5253 if (!use_register) {
5254 do_retry:
5255 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5256 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5257 usleep_range(1000, 2000);
5258 retry--;
5259 goto do_retry;
5260 }
5261 }
5262
5263
5264 if (status || use_register)
5265 val = rd32(hw, reg_addr);
5266
5267 return val;
5268 }
5269
5270
5271
5272
5273
5274
5275
5276
5277
5278
5279
5280 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5281 u32 reg_addr, u32 reg_val,
5282 struct i40e_asq_cmd_details *cmd_details)
5283 {
5284 struct i40e_aq_desc desc;
5285 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5286 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5287 i40e_status status;
5288
5289 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5290
5291 cmd->address = cpu_to_le32(reg_addr);
5292 cmd->value = cpu_to_le32(reg_val);
5293
5294 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5295
5296 return status;
5297 }
5298
5299
5300
5301
5302
5303
5304
5305 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5306 {
5307 i40e_status status = 0;
5308 bool use_register;
5309 int retry = 5;
5310
5311 use_register = (((hw->aq.api_maj_ver == 1) &&
5312 (hw->aq.api_min_ver < 5)) ||
5313 (hw->mac.type == I40E_MAC_X722));
5314 if (!use_register) {
5315 do_retry:
5316 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5317 reg_val, NULL);
5318 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5319 usleep_range(1000, 2000);
5320 retry--;
5321 goto do_retry;
5322 }
5323 }
5324
5325
5326 if (status || use_register)
5327 wr32(hw, reg_addr, reg_val);
5328 }
5329
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,
5342 u8 phy_select, u8 dev_addr,
5343 u32 reg_addr, u32 reg_val,
5344 struct i40e_asq_cmd_details *cmd_details)
5345 {
5346 struct i40e_aq_desc desc;
5347 struct i40e_aqc_phy_register_access *cmd =
5348 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5349 i40e_status status;
5350
5351 i40e_fill_default_direct_cmd_desc(&desc,
5352 i40e_aqc_opc_set_phy_register);
5353
5354 cmd->phy_interface = phy_select;
5355 cmd->dev_address = dev_addr;
5356 cmd->reg_address = cpu_to_le32(reg_addr);
5357 cmd->reg_value = cpu_to_le32(reg_val);
5358
5359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5360
5361 return status;
5362 }
5363
5364
5365
5366
5367
5368
5369
5370
5371
5372
5373
5374
5375 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,
5376 u8 phy_select, u8 dev_addr,
5377 u32 reg_addr, u32 *reg_val,
5378 struct i40e_asq_cmd_details *cmd_details)
5379 {
5380 struct i40e_aq_desc desc;
5381 struct i40e_aqc_phy_register_access *cmd =
5382 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5383 i40e_status status;
5384
5385 i40e_fill_default_direct_cmd_desc(&desc,
5386 i40e_aqc_opc_get_phy_register);
5387
5388 cmd->phy_interface = phy_select;
5389 cmd->dev_address = dev_addr;
5390 cmd->reg_address = cpu_to_le32(reg_addr);
5391
5392 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5393 if (!status)
5394 *reg_val = le32_to_cpu(cmd->reg_value);
5395
5396 return status;
5397 }
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407
5408
5409 enum
5410 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5411 u16 buff_size, u32 track_id,
5412 u32 *error_offset, u32 *error_info,
5413 struct i40e_asq_cmd_details *cmd_details)
5414 {
5415 struct i40e_aq_desc desc;
5416 struct i40e_aqc_write_personalization_profile *cmd =
5417 (struct i40e_aqc_write_personalization_profile *)
5418 &desc.params.raw;
5419 struct i40e_aqc_write_ddp_resp *resp;
5420 i40e_status status;
5421
5422 i40e_fill_default_direct_cmd_desc(&desc,
5423 i40e_aqc_opc_write_personalization_profile);
5424
5425 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5426 if (buff_size > I40E_AQ_LARGE_BUF)
5427 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5428
5429 desc.datalen = cpu_to_le16(buff_size);
5430
5431 cmd->profile_track_id = cpu_to_le32(track_id);
5432
5433 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5434 if (!status) {
5435 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5436 if (error_offset)
5437 *error_offset = le32_to_cpu(resp->error_offset);
5438 if (error_info)
5439 *error_info = le32_to_cpu(resp->error_info);
5440 }
5441
5442 return status;
5443 }
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453 enum
5454 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5455 u16 buff_size, u8 flags,
5456 struct i40e_asq_cmd_details *cmd_details)
5457 {
5458 struct i40e_aq_desc desc;
5459 struct i40e_aqc_get_applied_profiles *cmd =
5460 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5461 i40e_status status;
5462
5463 i40e_fill_default_direct_cmd_desc(&desc,
5464 i40e_aqc_opc_get_personalization_profile_list);
5465
5466 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5467 if (buff_size > I40E_AQ_LARGE_BUF)
5468 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5469 desc.datalen = cpu_to_le16(buff_size);
5470
5471 cmd->flags = flags;
5472
5473 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5474
5475 return status;
5476 }
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487 struct i40e_generic_seg_header *
5488 i40e_find_segment_in_package(u32 segment_type,
5489 struct i40e_package_header *pkg_hdr)
5490 {
5491 struct i40e_generic_seg_header *segment;
5492 u32 i;
5493
5494
5495 for (i = 0; i < pkg_hdr->segment_count; i++) {
5496 segment =
5497 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5498 pkg_hdr->segment_offset[i]);
5499
5500 if (segment->type == segment_type)
5501 return segment;
5502 }
5503
5504 return NULL;
5505 }
5506
5507
5508 #define I40E_SECTION_TABLE(profile, sec_tbl) \
5509 do { \
5510 struct i40e_profile_segment *p = (profile); \
5511 u32 count; \
5512 u32 *nvm; \
5513 count = p->device_table_count; \
5514 nvm = (u32 *)&p->device_table[count]; \
5515 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5516 } while (0)
5517
5518
5519 #define I40E_SECTION_HEADER(profile, offset) \
5520 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5521
5522
5523
5524
5525
5526
5527
5528
5529
5530
5531 struct i40e_profile_section_header *
5532 i40e_find_section_in_profile(u32 section_type,
5533 struct i40e_profile_segment *profile)
5534 {
5535 struct i40e_profile_section_header *sec;
5536 struct i40e_section_table *sec_tbl;
5537 u32 sec_off;
5538 u32 i;
5539
5540 if (profile->header.type != SEGMENT_TYPE_I40E)
5541 return NULL;
5542
5543 I40E_SECTION_TABLE(profile, sec_tbl);
5544
5545 for (i = 0; i < sec_tbl->section_count; i++) {
5546 sec_off = sec_tbl->section_offset[i];
5547 sec = I40E_SECTION_HEADER(profile, sec_off);
5548 if (sec->section.type == section_type)
5549 return sec;
5550 }
5551
5552 return NULL;
5553 }
5554
5555
5556
5557
5558
5559
5560 static enum
5561 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5562 struct i40e_profile_aq_section *aq)
5563 {
5564 i40e_status status;
5565 struct i40e_aq_desc desc;
5566 u8 *msg = NULL;
5567 u16 msglen;
5568
5569 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5570 desc.flags |= cpu_to_le16(aq->flags);
5571 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5572
5573 msglen = aq->datalen;
5574 if (msglen) {
5575 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5576 I40E_AQ_FLAG_RD));
5577 if (msglen > I40E_AQ_LARGE_BUF)
5578 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5579 desc.datalen = cpu_to_le16(msglen);
5580 msg = &aq->data[0];
5581 }
5582
5583 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5584
5585 if (status) {
5586 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5587 "unable to exec DDP AQ opcode %u, error %d\n",
5588 aq->opcode, status);
5589 return status;
5590 }
5591
5592
5593 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5594
5595 return 0;
5596 }
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607 static enum i40e_status_code
5608 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5609 u32 track_id, bool rollback)
5610 {
5611 struct i40e_profile_section_header *sec = NULL;
5612 i40e_status status = 0;
5613 struct i40e_section_table *sec_tbl;
5614 u32 vendor_dev_id;
5615 u32 dev_cnt;
5616 u32 sec_off;
5617 u32 i;
5618
5619 if (track_id == I40E_DDP_TRACKID_INVALID) {
5620 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5621 return I40E_NOT_SUPPORTED;
5622 }
5623
5624 dev_cnt = profile->device_table_count;
5625 for (i = 0; i < dev_cnt; i++) {
5626 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5627 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5628 hw->device_id == (vendor_dev_id & 0xFFFF))
5629 break;
5630 }
5631 if (dev_cnt && i == dev_cnt) {
5632 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5633 "Device doesn't support DDP\n");
5634 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5635 }
5636
5637 I40E_SECTION_TABLE(profile, sec_tbl);
5638
5639
5640 for (i = 0; i < sec_tbl->section_count; i++) {
5641 sec_off = sec_tbl->section_offset[i];
5642 sec = I40E_SECTION_HEADER(profile, sec_off);
5643 if (rollback) {
5644 if (sec->section.type == SECTION_TYPE_MMIO ||
5645 sec->section.type == SECTION_TYPE_AQ ||
5646 sec->section.type == SECTION_TYPE_RB_AQ) {
5647 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5648 "Not a roll-back package\n");
5649 return I40E_NOT_SUPPORTED;
5650 }
5651 } else {
5652 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5653 sec->section.type == SECTION_TYPE_RB_MMIO) {
5654 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5655 "Not an original package\n");
5656 return I40E_NOT_SUPPORTED;
5657 }
5658 }
5659 }
5660
5661 return status;
5662 }
5663
5664
5665
5666
5667
5668
5669
5670
5671
5672 enum i40e_status_code
5673 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5674 u32 track_id)
5675 {
5676 i40e_status status = 0;
5677 struct i40e_section_table *sec_tbl;
5678 struct i40e_profile_section_header *sec = NULL;
5679 struct i40e_profile_aq_section *ddp_aq;
5680 u32 section_size = 0;
5681 u32 offset = 0, info = 0;
5682 u32 sec_off;
5683 u32 i;
5684
5685 status = i40e_validate_profile(hw, profile, track_id, false);
5686 if (status)
5687 return status;
5688
5689 I40E_SECTION_TABLE(profile, sec_tbl);
5690
5691 for (i = 0; i < sec_tbl->section_count; i++) {
5692 sec_off = sec_tbl->section_offset[i];
5693 sec = I40E_SECTION_HEADER(profile, sec_off);
5694
5695 if (sec->section.type == SECTION_TYPE_AQ) {
5696 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5697 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5698 if (status) {
5699 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5700 "Failed to execute aq: section %d, opcode %u\n",
5701 i, ddp_aq->opcode);
5702 break;
5703 }
5704 sec->section.type = SECTION_TYPE_RB_AQ;
5705 }
5706
5707
5708 if (sec->section.type != SECTION_TYPE_MMIO)
5709 continue;
5710
5711 section_size = sec->section.size +
5712 sizeof(struct i40e_profile_section_header);
5713
5714
5715 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5716 track_id, &offset, &info, NULL);
5717 if (status) {
5718 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5719 "Failed to write profile: section %d, offset %d, info %d\n",
5720 i, offset, info);
5721 break;
5722 }
5723 }
5724 return status;
5725 }
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735 enum i40e_status_code
5736 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5737 u32 track_id)
5738 {
5739 struct i40e_profile_section_header *sec = NULL;
5740 i40e_status status = 0;
5741 struct i40e_section_table *sec_tbl;
5742 u32 offset = 0, info = 0;
5743 u32 section_size = 0;
5744 u32 sec_off;
5745 int i;
5746
5747 status = i40e_validate_profile(hw, profile, track_id, true);
5748 if (status)
5749 return status;
5750
5751 I40E_SECTION_TABLE(profile, sec_tbl);
5752
5753
5754 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5755 sec_off = sec_tbl->section_offset[i];
5756 sec = I40E_SECTION_HEADER(profile, sec_off);
5757
5758
5759 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5760 continue;
5761
5762 section_size = sec->section.size +
5763 sizeof(struct i40e_profile_section_header);
5764
5765
5766 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5767 track_id, &offset, &info, NULL);
5768 if (status) {
5769 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5770 "Failed to write profile: section %d, offset %d, info %d\n",
5771 i, offset, info);
5772 break;
5773 }
5774 }
5775 return status;
5776 }
5777
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787 enum i40e_status_code
5788 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5789 struct i40e_profile_segment *profile,
5790 u8 *profile_info_sec, u32 track_id)
5791 {
5792 i40e_status status = 0;
5793 struct i40e_profile_section_header *sec = NULL;
5794 struct i40e_profile_info *pinfo;
5795 u32 offset = 0, info = 0;
5796
5797 sec = (struct i40e_profile_section_header *)profile_info_sec;
5798 sec->tbl_size = 1;
5799 sec->data_end = sizeof(struct i40e_profile_section_header) +
5800 sizeof(struct i40e_profile_info);
5801 sec->section.type = SECTION_TYPE_INFO;
5802 sec->section.offset = sizeof(struct i40e_profile_section_header);
5803 sec->section.size = sizeof(struct i40e_profile_info);
5804 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5805 sec->section.offset);
5806 pinfo->track_id = track_id;
5807 pinfo->version = profile->version;
5808 pinfo->op = I40E_DDP_ADD_TRACKID;
5809 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5810
5811 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5812 track_id, &offset, &info, NULL);
5813
5814 return status;
5815 }
5816
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826
5827
5828
5829 enum i40e_status_code
5830 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5831 struct i40e_aqc_cloud_filters_element_data *filters,
5832 u8 filter_count)
5833 {
5834 struct i40e_aq_desc desc;
5835 struct i40e_aqc_add_remove_cloud_filters *cmd =
5836 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5837 enum i40e_status_code status;
5838 u16 buff_len;
5839
5840 i40e_fill_default_direct_cmd_desc(&desc,
5841 i40e_aqc_opc_add_cloud_filters);
5842
5843 buff_len = filter_count * sizeof(*filters);
5844 desc.datalen = cpu_to_le16(buff_len);
5845 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5846 cmd->num_filters = filter_count;
5847 cmd->seid = cpu_to_le16(seid);
5848
5849 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5850
5851 return status;
5852 }
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866 enum i40e_status_code
5867 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5868 struct i40e_aqc_cloud_filters_element_bb *filters,
5869 u8 filter_count)
5870 {
5871 struct i40e_aq_desc desc;
5872 struct i40e_aqc_add_remove_cloud_filters *cmd =
5873 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5874 i40e_status status;
5875 u16 buff_len;
5876 int i;
5877
5878 i40e_fill_default_direct_cmd_desc(&desc,
5879 i40e_aqc_opc_add_cloud_filters);
5880
5881 buff_len = filter_count * sizeof(*filters);
5882 desc.datalen = cpu_to_le16(buff_len);
5883 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5884 cmd->num_filters = filter_count;
5885 cmd->seid = cpu_to_le16(seid);
5886 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5887
5888 for (i = 0; i < filter_count; i++) {
5889 u16 tnl_type;
5890 u32 ti;
5891
5892 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5893 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5894 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5895
5896
5897
5898
5899
5900 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5901 ti = le32_to_cpu(filters[i].element.tenant_id);
5902 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5903 }
5904 }
5905
5906 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5907
5908 return status;
5909 }
5910
5911
5912
5913
5914
5915
5916
5917
5918
5919
5920
5921
5922
5923 enum i40e_status_code
5924 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5925 struct i40e_aqc_cloud_filters_element_data *filters,
5926 u8 filter_count)
5927 {
5928 struct i40e_aq_desc desc;
5929 struct i40e_aqc_add_remove_cloud_filters *cmd =
5930 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5931 enum i40e_status_code status;
5932 u16 buff_len;
5933
5934 i40e_fill_default_direct_cmd_desc(&desc,
5935 i40e_aqc_opc_remove_cloud_filters);
5936
5937 buff_len = filter_count * sizeof(*filters);
5938 desc.datalen = cpu_to_le16(buff_len);
5939 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5940 cmd->num_filters = filter_count;
5941 cmd->seid = cpu_to_le16(seid);
5942
5943 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5944
5945 return status;
5946 }
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960 enum i40e_status_code
5961 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5962 struct i40e_aqc_cloud_filters_element_bb *filters,
5963 u8 filter_count)
5964 {
5965 struct i40e_aq_desc desc;
5966 struct i40e_aqc_add_remove_cloud_filters *cmd =
5967 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5968 i40e_status status;
5969 u16 buff_len;
5970 int i;
5971
5972 i40e_fill_default_direct_cmd_desc(&desc,
5973 i40e_aqc_opc_remove_cloud_filters);
5974
5975 buff_len = filter_count * sizeof(*filters);
5976 desc.datalen = cpu_to_le16(buff_len);
5977 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5978 cmd->num_filters = filter_count;
5979 cmd->seid = cpu_to_le16(seid);
5980 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5981
5982 for (i = 0; i < filter_count; i++) {
5983 u16 tnl_type;
5984 u32 ti;
5985
5986 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5987 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5988 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5989
5990
5991
5992
5993
5994 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5995 ti = le32_to_cpu(filters[i].element.tenant_id);
5996 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5997 }
5998 }
5999
6000 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6001
6002 return status;
6003 }