root/drivers/net/ethernet/intel/ice/ice_type.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. ice_is_tc_ena
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2018, Intel Corporation. */
   3 
   4 #ifndef _ICE_TYPE_H_
   5 #define _ICE_TYPE_H_
   6 
   7 #define ICE_BYTES_PER_WORD      2
   8 #define ICE_BYTES_PER_DWORD     4
   9 
  10 #include "ice_status.h"
  11 #include "ice_hw_autogen.h"
  12 #include "ice_osdep.h"
  13 #include "ice_controlq.h"
  14 #include "ice_lan_tx_rx.h"
  15 #include "ice_flex_type.h"
  16 
  17 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
  18 {
  19         return test_bit(tc, &bitmap);
  20 }
  21 
  22 /* Driver always calls main vsi_handle first */
  23 #define ICE_MAIN_VSI_HANDLE             0
  24 
  25 /* debug masks - set these bits in hw->debug_mask to control output */
  26 #define ICE_DBG_INIT            BIT_ULL(1)
  27 #define ICE_DBG_FW_LOG          BIT_ULL(3)
  28 #define ICE_DBG_LINK            BIT_ULL(4)
  29 #define ICE_DBG_PHY             BIT_ULL(5)
  30 #define ICE_DBG_QCTX            BIT_ULL(6)
  31 #define ICE_DBG_NVM             BIT_ULL(7)
  32 #define ICE_DBG_LAN             BIT_ULL(8)
  33 #define ICE_DBG_SW              BIT_ULL(13)
  34 #define ICE_DBG_SCHED           BIT_ULL(14)
  35 #define ICE_DBG_PKG             BIT_ULL(16)
  36 #define ICE_DBG_RES             BIT_ULL(17)
  37 #define ICE_DBG_AQ_MSG          BIT_ULL(24)
  38 #define ICE_DBG_AQ_CMD          BIT_ULL(27)
  39 #define ICE_DBG_USER            BIT_ULL(31)
  40 
  41 enum ice_aq_res_ids {
  42         ICE_NVM_RES_ID = 1,
  43         ICE_SPD_RES_ID,
  44         ICE_CHANGE_LOCK_RES_ID,
  45         ICE_GLOBAL_CFG_LOCK_RES_ID
  46 };
  47 
  48 /* FW update timeout definitions are in milliseconds */
  49 #define ICE_NVM_TIMEOUT                 180000
  50 #define ICE_CHANGE_LOCK_TIMEOUT         1000
  51 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT     3000
  52 
  53 enum ice_aq_res_access_type {
  54         ICE_RES_READ = 1,
  55         ICE_RES_WRITE
  56 };
  57 
  58 struct ice_driver_ver {
  59         u8 major_ver;
  60         u8 minor_ver;
  61         u8 build_ver;
  62         u8 subbuild_ver;
  63         u8 driver_string[32];
  64 };
  65 
  66 enum ice_fc_mode {
  67         ICE_FC_NONE = 0,
  68         ICE_FC_RX_PAUSE,
  69         ICE_FC_TX_PAUSE,
  70         ICE_FC_FULL,
  71         ICE_FC_PFC,
  72         ICE_FC_DFLT
  73 };
  74 
  75 enum ice_fec_mode {
  76         ICE_FEC_NONE = 0,
  77         ICE_FEC_RS,
  78         ICE_FEC_BASER,
  79         ICE_FEC_AUTO
  80 };
  81 
  82 enum ice_set_fc_aq_failures {
  83         ICE_SET_FC_AQ_FAIL_NONE = 0,
  84         ICE_SET_FC_AQ_FAIL_GET,
  85         ICE_SET_FC_AQ_FAIL_SET,
  86         ICE_SET_FC_AQ_FAIL_UPDATE
  87 };
  88 
  89 /* Various MAC types */
  90 enum ice_mac_type {
  91         ICE_MAC_UNKNOWN = 0,
  92         ICE_MAC_GENERIC,
  93 };
  94 
  95 /* Media Types */
  96 enum ice_media_type {
  97         ICE_MEDIA_UNKNOWN = 0,
  98         ICE_MEDIA_FIBER,
  99         ICE_MEDIA_BASET,
 100         ICE_MEDIA_BACKPLANE,
 101         ICE_MEDIA_DA,
 102 };
 103 
 104 enum ice_vsi_type {
 105         ICE_VSI_PF = 0,
 106         ICE_VSI_VF,
 107         ICE_VSI_LB = 6,
 108 };
 109 
 110 struct ice_link_status {
 111         /* Refer to ice_aq_phy_type for bits definition */
 112         u64 phy_type_low;
 113         u64 phy_type_high;
 114         u8 topo_media_conflict;
 115         u16 max_frame_size;
 116         u16 link_speed;
 117         u16 req_speeds;
 118         u8 lse_ena;     /* Link Status Event notification */
 119         u8 link_info;
 120         u8 an_info;
 121         u8 ext_info;
 122         u8 fec_info;
 123         u8 pacing;
 124         /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
 125          * ice_aqc_get_phy_caps structure
 126          */
 127         u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
 128 };
 129 
 130 /* Different reset sources for which a disable queue AQ call has to be made in
 131  * order to clean the Tx scheduler as a part of the reset
 132  */
 133 enum ice_disq_rst_src {
 134         ICE_NO_RESET = 0,
 135         ICE_VM_RESET,
 136         ICE_VF_RESET,
 137 };
 138 
 139 /* PHY info such as phy_type, etc... */
 140 struct ice_phy_info {
 141         struct ice_link_status link_info;
 142         struct ice_link_status link_info_old;
 143         u64 phy_type_low;
 144         u64 phy_type_high;
 145         enum ice_media_type media_type;
 146         u8 get_link_info;
 147 };
 148 
 149 /* Common HW capabilities for SW use */
 150 struct ice_hw_common_caps {
 151         u32 valid_functions;
 152         /* DCB capabilities */
 153         u32 active_tc_bitmap;
 154         u32 maxtc;
 155 
 156         /* Tx/Rx queues */
 157         u16 num_rxq;            /* Number/Total Rx queues */
 158         u16 rxq_first_id;       /* First queue ID for Rx queues */
 159         u16 num_txq;            /* Number/Total Tx queues */
 160         u16 txq_first_id;       /* First queue ID for Tx queues */
 161 
 162         /* MSI-X vectors */
 163         u16 num_msix_vectors;
 164         u16 msix_vector_first_id;
 165 
 166         /* Max MTU for function or device */
 167         u16 max_mtu;
 168 
 169         /* Virtualization support */
 170         u8 sr_iov_1_1;                  /* SR-IOV enabled */
 171 
 172         /* RSS related capabilities */
 173         u16 rss_table_size;             /* 512 for PFs and 64 for VFs */
 174         u8 rss_table_entry_width;       /* RSS Entry width in bits */
 175 
 176         u8 dcb;
 177 };
 178 
 179 /* Function specific capabilities */
 180 struct ice_hw_func_caps {
 181         struct ice_hw_common_caps common_cap;
 182         u32 num_allocd_vfs;             /* Number of allocated VFs */
 183         u32 vf_base_id;                 /* Logical ID of the first VF */
 184         u32 guar_num_vsi;
 185 };
 186 
 187 /* Device wide capabilities */
 188 struct ice_hw_dev_caps {
 189         struct ice_hw_common_caps common_cap;
 190         u32 num_vfs_exposed;            /* Total number of VFs exposed */
 191         u32 num_vsi_allocd_to_host;     /* Excluding EMP VSI */
 192 };
 193 
 194 /* MAC info */
 195 struct ice_mac_info {
 196         u8 lan_addr[ETH_ALEN];
 197         u8 perm_addr[ETH_ALEN];
 198 };
 199 
 200 /* Reset types used to determine which kind of reset was requested. These
 201  * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
 202  * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
 203  * because its reset source is different than the other types listed.
 204  */
 205 enum ice_reset_req {
 206         ICE_RESET_POR   = 0,
 207         ICE_RESET_INVAL = 0,
 208         ICE_RESET_CORER = 1,
 209         ICE_RESET_GLOBR = 2,
 210         ICE_RESET_EMPR  = 3,
 211         ICE_RESET_PFR   = 4,
 212 };
 213 
 214 /* Bus parameters */
 215 struct ice_bus_info {
 216         u16 device;
 217         u8 func;
 218 };
 219 
 220 /* Flow control (FC) parameters */
 221 struct ice_fc_info {
 222         enum ice_fc_mode current_mode;  /* FC mode in effect */
 223         enum ice_fc_mode req_mode;      /* FC mode requested by caller */
 224 };
 225 
 226 /* NVM Information */
 227 struct ice_nvm_info {
 228         u32 eetrack;              /* NVM data version */
 229         u32 oem_ver;              /* OEM version info */
 230         u16 sr_words;             /* Shadow RAM size in words */
 231         u16 ver;                  /* NVM package version */
 232         u8 blank_nvm_mode;        /* is NVM empty (no FW present) */
 233 };
 234 
 235 #define ICE_NVM_VER_LEN 32
 236 
 237 /* Max number of port to queue branches w.r.t topology */
 238 #define ICE_MAX_TRAFFIC_CLASS 8
 239 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
 240 
 241 #define ice_for_each_traffic_class(_i)  \
 242         for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
 243 
 244 #define ICE_INVAL_TEID 0xFFFFFFFF
 245 
 246 struct ice_sched_node {
 247         struct ice_sched_node *parent;
 248         struct ice_sched_node *sibling; /* next sibling in the same layer */
 249         struct ice_sched_node **children;
 250         struct ice_aqc_txsched_elem_data info;
 251         u32 agg_id;                     /* aggregator group ID */
 252         u16 vsi_handle;
 253         u8 in_use;                      /* suspended or in use */
 254         u8 tx_sched_layer;              /* Logical Layer (1-9) */
 255         u8 num_children;
 256         u8 tc_num;
 257         u8 owner;
 258 #define ICE_SCHED_NODE_OWNER_LAN        0
 259 };
 260 
 261 /* Access Macros for Tx Sched Elements data */
 262 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
 263 
 264 /* The aggregator type determines if identifier is for a VSI group,
 265  * aggregator group, aggregator of queues, or queue group.
 266  */
 267 enum ice_agg_type {
 268         ICE_AGG_TYPE_UNKNOWN = 0,
 269         ICE_AGG_TYPE_VSI,
 270         ICE_AGG_TYPE_AGG, /* aggregator */
 271         ICE_AGG_TYPE_Q,
 272         ICE_AGG_TYPE_QG
 273 };
 274 
 275 #define ICE_SCHED_DFLT_RL_PROF_ID       0
 276 #define ICE_SCHED_DFLT_BW_WT            1
 277 
 278 /* VSI type list entry to locate corresponding VSI/ag nodes */
 279 struct ice_sched_vsi_info {
 280         struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
 281         struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
 282         struct list_head list_entry;
 283         u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
 284 };
 285 
 286 /* driver defines the policy */
 287 struct ice_sched_tx_policy {
 288         u16 max_num_vsis;
 289         u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
 290         u8 rdma_ena;
 291 };
 292 
 293 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 294 struct ice_dcb_ets_cfg {
 295         u8 willing;
 296         u8 cbs;
 297         u8 maxtcs;
 298         u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
 299         u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
 300         u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
 301 };
 302 
 303 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 304 struct ice_dcb_pfc_cfg {
 305         u8 willing;
 306         u8 mbc;
 307         u8 pfccap;
 308         u8 pfcena;
 309 };
 310 
 311 /* CEE or IEEE 802.1Qaz Application Priority data */
 312 struct ice_dcb_app_priority_table {
 313         u16 prot_id;
 314         u8 priority;
 315         u8 selector;
 316 };
 317 
 318 #define ICE_MAX_USER_PRIORITY   8
 319 #define ICE_DCBX_MAX_APPS       32
 320 #define ICE_LLDPDU_SIZE         1500
 321 #define ICE_TLV_STATUS_OPER     0x1
 322 #define ICE_TLV_STATUS_SYNC     0x2
 323 #define ICE_TLV_STATUS_ERR      0x4
 324 #define ICE_APP_PROT_ID_FCOE    0x8906
 325 #define ICE_APP_PROT_ID_ISCSI   0x0cbc
 326 #define ICE_APP_PROT_ID_FIP     0x8914
 327 #define ICE_APP_SEL_ETHTYPE     0x1
 328 #define ICE_APP_SEL_TCPIP       0x2
 329 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
 330 #define ICE_CEE_APP_SEL_TCPIP   0x1
 331 
 332 struct ice_dcbx_cfg {
 333         u32 numapps;
 334         u32 tlv_status; /* CEE mode TLV status */
 335         struct ice_dcb_ets_cfg etscfg;
 336         struct ice_dcb_ets_cfg etsrec;
 337         struct ice_dcb_pfc_cfg pfc;
 338         struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
 339         u8 dcbx_mode;
 340 #define ICE_DCBX_MODE_CEE       0x1
 341 #define ICE_DCBX_MODE_IEEE      0x2
 342         u8 app_mode;
 343 #define ICE_DCBX_APPS_NON_WILLING       0x1
 344 };
 345 
 346 struct ice_port_info {
 347         struct ice_sched_node *root;    /* Root Node per Port */
 348         struct ice_hw *hw;              /* back pointer to HW instance */
 349         u32 last_node_teid;             /* scheduler last node info */
 350         u16 sw_id;                      /* Initial switch ID belongs to port */
 351         u16 pf_vf_num;
 352         u8 port_state;
 353 #define ICE_SCHED_PORT_STATE_INIT       0x0
 354 #define ICE_SCHED_PORT_STATE_READY      0x1
 355         u8 lport;
 356 #define ICE_LPORT_MASK                  0xff
 357         u16 dflt_tx_vsi_rule_id;
 358         u16 dflt_tx_vsi_num;
 359         u16 dflt_rx_vsi_rule_id;
 360         u16 dflt_rx_vsi_num;
 361         struct ice_fc_info fc;
 362         struct ice_mac_info mac;
 363         struct ice_phy_info phy;
 364         struct mutex sched_lock;        /* protect access to TXSched tree */
 365         struct ice_sched_node *
 366                 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
 367         struct ice_dcbx_cfg local_dcbx_cfg;     /* Oper/Local Cfg */
 368         /* DCBX info */
 369         struct ice_dcbx_cfg remote_dcbx_cfg;    /* Peer Cfg */
 370         struct ice_dcbx_cfg desired_dcbx_cfg;   /* CEE Desired Cfg */
 371         /* LLDP/DCBX Status */
 372         u8 dcbx_status:3;               /* see ICE_DCBX_STATUS_DIS */
 373         u8 is_sw_lldp:1;
 374         u8 is_vf:1;
 375 };
 376 
 377 struct ice_switch_info {
 378         struct list_head vsi_list_map_head;
 379         struct ice_sw_recipe *recp_list;
 380 };
 381 
 382 /* FW logging configuration */
 383 struct ice_fw_log_evnt {
 384         u8 cfg : 4;     /* New event enables to configure */
 385         u8 cur : 4;     /* Current/active event enables */
 386 };
 387 
 388 struct ice_fw_log_cfg {
 389         u8 cq_en : 1;    /* FW logging is enabled via the control queue */
 390         u8 uart_en : 1;  /* FW logging is enabled via UART for all PFs */
 391         u8 actv_evnts;   /* Cumulation of currently enabled log events */
 392 
 393 #define ICE_FW_LOG_EVNT_INFO    (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
 394 #define ICE_FW_LOG_EVNT_INIT    (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
 395 #define ICE_FW_LOG_EVNT_FLOW    (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
 396 #define ICE_FW_LOG_EVNT_ERR     (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
 397         struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
 398 };
 399 
 400 /* Port hardware description */
 401 struct ice_hw {
 402         u8 __iomem *hw_addr;
 403         void *back;
 404         struct ice_aqc_layer_props *layer_info;
 405         struct ice_port_info *port_info;
 406         u64 debug_mask;         /* bitmap for debug mask */
 407         enum ice_mac_type mac_type;
 408 
 409         /* pci info */
 410         u16 device_id;
 411         u16 vendor_id;
 412         u16 subsystem_device_id;
 413         u16 subsystem_vendor_id;
 414         u8 revision_id;
 415 
 416         u8 pf_id;               /* device profile info */
 417 
 418         /* Tx Scheduler values */
 419         u16 num_tx_sched_layers;
 420         u16 num_tx_sched_phys_layers;
 421         u8 flattened_layers;
 422         u8 max_cgds;
 423         u8 sw_entry_point_layer;
 424         u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
 425         struct list_head agg_list;      /* lists all aggregator */
 426 
 427         struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
 428         u8 evb_veb;             /* true for VEB, false for VEPA */
 429         u8 reset_ongoing;       /* true if HW is in reset, false otherwise */
 430         struct ice_bus_info bus;
 431         struct ice_nvm_info nvm;
 432         struct ice_hw_dev_caps dev_caps;        /* device capabilities */
 433         struct ice_hw_func_caps func_caps;      /* function capabilities */
 434 
 435         struct ice_switch_info *switch_info;    /* switch filter lists */
 436 
 437         /* Control Queue info */
 438         struct ice_ctl_q_info adminq;
 439         struct ice_ctl_q_info mailboxq;
 440 
 441         u8 api_branch;          /* API branch version */
 442         u8 api_maj_ver;         /* API major version */
 443         u8 api_min_ver;         /* API minor version */
 444         u8 api_patch;           /* API patch version */
 445         u8 fw_branch;           /* firmware branch version */
 446         u8 fw_maj_ver;          /* firmware major version */
 447         u8 fw_min_ver;          /* firmware minor version */
 448         u8 fw_patch;            /* firmware patch version */
 449         u32 fw_build;           /* firmware build number */
 450 
 451         struct ice_fw_log_cfg fw_log;
 452 
 453 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
 454  * register. Used for determining the ITR/intrl granularity during
 455  * initialization.
 456  */
 457 #define ICE_MAX_AGG_BW_200G     0x0
 458 #define ICE_MAX_AGG_BW_100G     0X1
 459 #define ICE_MAX_AGG_BW_50G      0x2
 460 #define ICE_MAX_AGG_BW_25G      0x3
 461         /* ITR granularity for different speeds */
 462 #define ICE_ITR_GRAN_ABOVE_25   2
 463 #define ICE_ITR_GRAN_MAX_25     4
 464         /* ITR granularity in 1 us */
 465         u8 itr_gran;
 466         /* INTRL granularity for different speeds */
 467 #define ICE_INTRL_GRAN_ABOVE_25 4
 468 #define ICE_INTRL_GRAN_MAX_25   8
 469         /* INTRL granularity in 1 us */
 470         u8 intrl_gran;
 471 
 472         u8 ucast_shared;        /* true if VSIs can share unicast addr */
 473 
 474         /* Active package version (currently active) */
 475         struct ice_pkg_ver active_pkg_ver;
 476         u8 active_pkg_name[ICE_PKG_NAME_SIZE];
 477         u8 active_pkg_in_nvm;
 478 
 479         enum ice_aq_err pkg_dwnld_status;
 480 
 481         /* Driver's package ver - (from the Metadata seg) */
 482         struct ice_pkg_ver pkg_ver;
 483         u8 pkg_name[ICE_PKG_NAME_SIZE];
 484 
 485         /* Driver's Ice package version (from the Ice seg) */
 486         struct ice_pkg_ver ice_pkg_ver;
 487         u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
 488 
 489         /* Pointer to the ice segment */
 490         struct ice_seg *seg;
 491 
 492         /* Pointer to allocated copy of pkg memory */
 493         u8 *pkg_copy;
 494         u32 pkg_size;
 495 
 496         /* HW block tables */
 497         struct ice_blk_info blk[ICE_BLK_COUNT];
 498 };
 499 
 500 /* Statistics collected by each port, VSI, VEB, and S-channel */
 501 struct ice_eth_stats {
 502         u64 rx_bytes;                   /* gorc */
 503         u64 rx_unicast;                 /* uprc */
 504         u64 rx_multicast;               /* mprc */
 505         u64 rx_broadcast;               /* bprc */
 506         u64 rx_discards;                /* rdpc */
 507         u64 rx_unknown_protocol;        /* rupp */
 508         u64 tx_bytes;                   /* gotc */
 509         u64 tx_unicast;                 /* uptc */
 510         u64 tx_multicast;               /* mptc */
 511         u64 tx_broadcast;               /* bptc */
 512         u64 tx_discards;                /* tdpc */
 513         u64 tx_errors;                  /* tepc */
 514 };
 515 
 516 /* Statistics collected by the MAC */
 517 struct ice_hw_port_stats {
 518         /* eth stats collected by the port */
 519         struct ice_eth_stats eth;
 520         /* additional port specific stats */
 521         u64 tx_dropped_link_down;       /* tdold */
 522         u64 crc_errors;                 /* crcerrs */
 523         u64 illegal_bytes;              /* illerrc */
 524         u64 error_bytes;                /* errbc */
 525         u64 mac_local_faults;           /* mlfc */
 526         u64 mac_remote_faults;          /* mrfc */
 527         u64 rx_len_errors;              /* rlec */
 528         u64 link_xon_rx;                /* lxonrxc */
 529         u64 link_xoff_rx;               /* lxoffrxc */
 530         u64 link_xon_tx;                /* lxontxc */
 531         u64 link_xoff_tx;               /* lxofftxc */
 532         u64 priority_xon_rx[8];         /* pxonrxc[8] */
 533         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
 534         u64 priority_xon_tx[8];         /* pxontxc[8] */
 535         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
 536         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
 537         u64 rx_size_64;                 /* prc64 */
 538         u64 rx_size_127;                /* prc127 */
 539         u64 rx_size_255;                /* prc255 */
 540         u64 rx_size_511;                /* prc511 */
 541         u64 rx_size_1023;               /* prc1023 */
 542         u64 rx_size_1522;               /* prc1522 */
 543         u64 rx_size_big;                /* prc9522 */
 544         u64 rx_undersize;               /* ruc */
 545         u64 rx_fragments;               /* rfc */
 546         u64 rx_oversize;                /* roc */
 547         u64 rx_jabber;                  /* rjc */
 548         u64 tx_size_64;                 /* ptc64 */
 549         u64 tx_size_127;                /* ptc127 */
 550         u64 tx_size_255;                /* ptc255 */
 551         u64 tx_size_511;                /* ptc511 */
 552         u64 tx_size_1023;               /* ptc1023 */
 553         u64 tx_size_1522;               /* ptc1522 */
 554         u64 tx_size_big;                /* ptc9522 */
 555 };
 556 
 557 /* Checksum and Shadow RAM pointers */
 558 #define ICE_SR_NVM_DEV_STARTER_VER      0x18
 559 #define ICE_SR_NVM_EETRACK_LO           0x2D
 560 #define ICE_SR_NVM_EETRACK_HI           0x2E
 561 #define ICE_NVM_VER_LO_SHIFT            0
 562 #define ICE_NVM_VER_LO_MASK             (0xff << ICE_NVM_VER_LO_SHIFT)
 563 #define ICE_NVM_VER_HI_SHIFT            12
 564 #define ICE_NVM_VER_HI_MASK             (0xf << ICE_NVM_VER_HI_SHIFT)
 565 #define ICE_OEM_VER_PATCH_SHIFT         0
 566 #define ICE_OEM_VER_PATCH_MASK          (0xff << ICE_OEM_VER_PATCH_SHIFT)
 567 #define ICE_OEM_VER_BUILD_SHIFT         8
 568 #define ICE_OEM_VER_BUILD_MASK          (0xffff << ICE_OEM_VER_BUILD_SHIFT)
 569 #define ICE_OEM_VER_SHIFT               24
 570 #define ICE_OEM_VER_MASK                (0xff << ICE_OEM_VER_SHIFT)
 571 #define ICE_SR_SECTOR_SIZE_IN_WORDS     0x800
 572 #define ICE_SR_WORDS_IN_1KB             512
 573 
 574 /* Hash redirection LUT for VSI - maximum array size */
 575 #define ICE_VSIQF_HLUT_ARRAY_SIZE       ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
 576 
 577 #endif /* _ICE_TYPE_H_ */
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