This source file includes following definitions.
- sis900_get_mac_addr
- sis630e_get_mac_addr
- sis635_get_mac_addr
- sis96x_get_mac_addr
- sis900_probe
- sis900_mii_probe
- sis900_default_phy
- sis900_set_capability
- read_eeprom
- mdio_idle
- mdio_reset
- mdio_read
- mdio_write
- sis900_reset_phy
- sis900_poll
- sis900_open
- sis900_init_rxfilter
- sis900_init_tx_ring
- sis900_init_rx_ring
- sis630_set_eq
- sis900_timer
- sis900_check_mode
- sis900_set_mode
- sis900_auto_negotiate
- sis900_read_mode
- sis900_tx_timeout
- sis900_start_xmit
- sis900_interrupt
- sis900_rx
- sis900_finish_xmit
- sis900_close
- sis900_get_drvinfo
- sis900_get_msglevel
- sis900_set_msglevel
- sis900_get_link
- sis900_get_link_ksettings
- sis900_set_link_ksettings
- sis900_nway_reset
- sis900_set_wol
- sis900_get_wol
- sis900_get_eeprom_len
- sis900_read_eeprom
- sis900_get_eeprom
- mii_ioctl
- sis900_set_config
- sis900_mcast_bitnr
- set_rx_mode
- sis900_reset
- sis900_remove
- sis900_suspend
- sis900_resume
- sis900_init_module
- sis900_cleanup_module
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52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/sched.h>
56 #include <linux/string.h>
57 #include <linux/timer.h>
58 #include <linux/errno.h>
59 #include <linux/ioport.h>
60 #include <linux/slab.h>
61 #include <linux/interrupt.h>
62 #include <linux/pci.h>
63 #include <linux/netdevice.h>
64 #include <linux/init.h>
65 #include <linux/mii.h>
66 #include <linux/etherdevice.h>
67 #include <linux/skbuff.h>
68 #include <linux/delay.h>
69 #include <linux/ethtool.h>
70 #include <linux/crc32.h>
71 #include <linux/bitops.h>
72 #include <linux/dma-mapping.h>
73
74 #include <asm/processor.h>
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <linux/uaccess.h>
78
79 #include "sis900.h"
80
81 #define SIS900_MODULE_NAME "sis900"
82 #define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
83
84 static const char version[] =
85 KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
86
87 static int max_interrupt_work = 40;
88 static int multicast_filter_limit = 128;
89
90 static int sis900_debug = -1;
91
92 #define SIS900_DEF_MSG \
93 (NETIF_MSG_DRV | \
94 NETIF_MSG_LINK | \
95 NETIF_MSG_RX_ERR | \
96 NETIF_MSG_TX_ERR)
97
98
99 #define TX_TIMEOUT (4*HZ)
100
101 enum {
102 SIS_900 = 0,
103 SIS_7016
104 };
105 static const char * card_names[] = {
106 "SiS 900 PCI Fast Ethernet",
107 "SiS 7016 PCI Fast Ethernet"
108 };
109
110 static const struct pci_device_id sis900_pci_tbl[] = {
111 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_900,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_900},
113 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7016,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_7016},
115 {0,}
116 };
117 MODULE_DEVICE_TABLE (pci, sis900_pci_tbl);
118
119 static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex);
120
121 static const struct mii_chip_info {
122 const char * name;
123 u16 phy_id0;
124 u16 phy_id1;
125 u8 phy_types;
126 #define HOME 0x0001
127 #define LAN 0x0002
128 #define MIX 0x0003
129 #define UNKNOWN 0x0
130 } mii_chip_table[] = {
131 { "SiS 900 Internal MII PHY", 0x001d, 0x8000, LAN },
132 { "SiS 7014 Physical Layer Solution", 0x0016, 0xf830, LAN },
133 { "SiS 900 on Foxconn 661 7MI", 0x0143, 0xBC70, LAN },
134 { "Altimata AC101LF PHY", 0x0022, 0x5520, LAN },
135 { "ADM 7001 LAN PHY", 0x002e, 0xcc60, LAN },
136 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
137 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME},
138 { "ICS LAN PHY", 0x0015, 0xF440, LAN },
139 { "ICS LAN PHY", 0x0143, 0xBC70, LAN },
140 { "NS 83851 PHY", 0x2000, 0x5C20, MIX },
141 { "NS 83847 PHY", 0x2000, 0x5C30, MIX },
142 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN },
143 { "VIA 6103 PHY", 0x0101, 0x8f20, LAN },
144 {NULL,},
145 };
146
147 struct mii_phy {
148 struct mii_phy * next;
149 int phy_addr;
150 u16 phy_id0;
151 u16 phy_id1;
152 u16 status;
153 u8 phy_types;
154 };
155
156 typedef struct _BufferDesc {
157 u32 link;
158 u32 cmdsts;
159 u32 bufptr;
160 } BufferDesc;
161
162 struct sis900_private {
163 struct pci_dev * pci_dev;
164
165 spinlock_t lock;
166
167 struct mii_phy * mii;
168 struct mii_phy * first_mii;
169 unsigned int cur_phy;
170 struct mii_if_info mii_info;
171
172 void __iomem *ioaddr;
173
174 struct timer_list timer;
175 u8 autong_complete;
176
177 u32 msg_enable;
178
179 unsigned int cur_rx, dirty_rx;
180 unsigned int cur_tx, dirty_tx;
181
182
183 struct sk_buff *tx_skbuff[NUM_TX_DESC];
184 struct sk_buff *rx_skbuff[NUM_RX_DESC];
185 BufferDesc *tx_ring;
186 BufferDesc *rx_ring;
187
188 dma_addr_t tx_ring_dma;
189 dma_addr_t rx_ring_dma;
190
191 unsigned int tx_full;
192 u8 host_bridge_rev;
193 u8 chipset_rev;
194
195 int eeprom_size;
196 };
197
198 MODULE_AUTHOR("Jim Huang <cmhuang@sis.com.tw>, Ollie Lho <ollie@sis.com.tw>");
199 MODULE_DESCRIPTION("SiS 900 PCI Fast Ethernet driver");
200 MODULE_LICENSE("GPL");
201
202 module_param(multicast_filter_limit, int, 0444);
203 module_param(max_interrupt_work, int, 0444);
204 module_param(sis900_debug, int, 0444);
205 MODULE_PARM_DESC(multicast_filter_limit, "SiS 900/7016 maximum number of filtered multicast addresses");
206 MODULE_PARM_DESC(max_interrupt_work, "SiS 900/7016 maximum events handled per interrupt");
207 MODULE_PARM_DESC(sis900_debug, "SiS 900/7016 bitmapped debugging message level");
208
209 #define sw32(reg, val) iowrite32(val, ioaddr + (reg))
210 #define sw8(reg, val) iowrite8(val, ioaddr + (reg))
211 #define sr32(reg) ioread32(ioaddr + (reg))
212 #define sr16(reg) ioread16(ioaddr + (reg))
213
214 #ifdef CONFIG_NET_POLL_CONTROLLER
215 static void sis900_poll(struct net_device *dev);
216 #endif
217 static int sis900_open(struct net_device *net_dev);
218 static int sis900_mii_probe (struct net_device * net_dev);
219 static void sis900_init_rxfilter (struct net_device * net_dev);
220 static u16 read_eeprom(void __iomem *ioaddr, int location);
221 static int mdio_read(struct net_device *net_dev, int phy_id, int location);
222 static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val);
223 static void sis900_timer(struct timer_list *t);
224 static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy);
225 static void sis900_tx_timeout(struct net_device *net_dev);
226 static void sis900_init_tx_ring(struct net_device *net_dev);
227 static void sis900_init_rx_ring(struct net_device *net_dev);
228 static netdev_tx_t sis900_start_xmit(struct sk_buff *skb,
229 struct net_device *net_dev);
230 static int sis900_rx(struct net_device *net_dev);
231 static void sis900_finish_xmit (struct net_device *net_dev);
232 static irqreturn_t sis900_interrupt(int irq, void *dev_instance);
233 static int sis900_close(struct net_device *net_dev);
234 static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd);
235 static u16 sis900_mcast_bitnr(u8 *addr, u8 revision);
236 static void set_rx_mode(struct net_device *net_dev);
237 static void sis900_reset(struct net_device *net_dev);
238 static void sis630_set_eq(struct net_device *net_dev, u8 revision);
239 static int sis900_set_config(struct net_device *dev, struct ifmap *map);
240 static u16 sis900_default_phy(struct net_device * net_dev);
241 static void sis900_set_capability( struct net_device *net_dev ,struct mii_phy *phy);
242 static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr);
243 static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr);
244 static void sis900_set_mode(struct sis900_private *, int speed, int duplex);
245 static const struct ethtool_ops sis900_ethtool_ops;
246
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255
256 static int sis900_get_mac_addr(struct pci_dev *pci_dev,
257 struct net_device *net_dev)
258 {
259 struct sis900_private *sis_priv = netdev_priv(net_dev);
260 void __iomem *ioaddr = sis_priv->ioaddr;
261 u16 signature;
262 int i;
263
264
265 signature = (u16) read_eeprom(ioaddr, EEPROMSignature);
266 if (signature == 0xffff || signature == 0x0000) {
267 printk (KERN_WARNING "%s: Error EEPROM read %x\n",
268 pci_name(pci_dev), signature);
269 return 0;
270 }
271
272
273 for (i = 0; i < 3; i++)
274 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
275
276 return 1;
277 }
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287
288
289 static int sis630e_get_mac_addr(struct pci_dev *pci_dev,
290 struct net_device *net_dev)
291 {
292 struct pci_dev *isa_bridge = NULL;
293 u8 reg;
294 int i;
295
296 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, isa_bridge);
297 if (!isa_bridge)
298 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0018, isa_bridge);
299 if (!isa_bridge) {
300 printk(KERN_WARNING "%s: Can not find ISA bridge\n",
301 pci_name(pci_dev));
302 return 0;
303 }
304 pci_read_config_byte(isa_bridge, 0x48, ®);
305 pci_write_config_byte(isa_bridge, 0x48, reg | 0x40);
306
307 for (i = 0; i < 6; i++) {
308 outb(0x09 + i, 0x70);
309 ((u8 *)(net_dev->dev_addr))[i] = inb(0x71);
310 }
311
312 pci_write_config_byte(isa_bridge, 0x48, reg & ~0x40);
313 pci_dev_put(isa_bridge);
314
315 return 1;
316 }
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328
329 static int sis635_get_mac_addr(struct pci_dev *pci_dev,
330 struct net_device *net_dev)
331 {
332 struct sis900_private *sis_priv = netdev_priv(net_dev);
333 void __iomem *ioaddr = sis_priv->ioaddr;
334 u32 rfcrSave;
335 u32 i;
336
337 rfcrSave = sr32(rfcr);
338
339 sw32(cr, rfcrSave | RELOAD);
340 sw32(cr, 0);
341
342
343 sw32(rfcr, rfcrSave & ~RFEN);
344
345
346 for (i = 0 ; i < 3 ; i++) {
347 sw32(rfcr, (i << RFADDR_shift));
348 *( ((u16 *)net_dev->dev_addr) + i) = sr16(rfdr);
349 }
350
351
352 sw32(rfcr, rfcrSave | RFEN);
353
354 return 1;
355 }
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372
373 static int sis96x_get_mac_addr(struct pci_dev *pci_dev,
374 struct net_device *net_dev)
375 {
376 struct sis900_private *sis_priv = netdev_priv(net_dev);
377 void __iomem *ioaddr = sis_priv->ioaddr;
378 int wait, rc = 0;
379
380 sw32(mear, EEREQ);
381 for (wait = 0; wait < 2000; wait++) {
382 if (sr32(mear) & EEGNT) {
383 u16 *mac = (u16 *)net_dev->dev_addr;
384 int i;
385
386
387 for (i = 0; i < 3; i++)
388 mac[i] = read_eeprom(ioaddr, i + EEPROMMACAddr);
389
390 rc = 1;
391 break;
392 }
393 udelay(1);
394 }
395 sw32(mear, EEDONE);
396 return rc;
397 }
398
399 static const struct net_device_ops sis900_netdev_ops = {
400 .ndo_open = sis900_open,
401 .ndo_stop = sis900_close,
402 .ndo_start_xmit = sis900_start_xmit,
403 .ndo_set_config = sis900_set_config,
404 .ndo_set_rx_mode = set_rx_mode,
405 .ndo_validate_addr = eth_validate_addr,
406 .ndo_set_mac_address = eth_mac_addr,
407 .ndo_do_ioctl = mii_ioctl,
408 .ndo_tx_timeout = sis900_tx_timeout,
409 #ifdef CONFIG_NET_POLL_CONTROLLER
410 .ndo_poll_controller = sis900_poll,
411 #endif
412 };
413
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423
424
425 static int sis900_probe(struct pci_dev *pci_dev,
426 const struct pci_device_id *pci_id)
427 {
428 struct sis900_private *sis_priv;
429 struct net_device *net_dev;
430 struct pci_dev *dev;
431 dma_addr_t ring_dma;
432 void *ring_space;
433 void __iomem *ioaddr;
434 int i, ret;
435 const char *card_name = card_names[pci_id->driver_data];
436 const char *dev_name = pci_name(pci_dev);
437
438
439 #ifndef MODULE
440 static int printed_version;
441 if (!printed_version++)
442 printk(version);
443 #endif
444
445
446 ret = pci_enable_device(pci_dev);
447 if(ret) return ret;
448
449 i = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
450 if(i){
451 printk(KERN_ERR "sis900.c: architecture does not support "
452 "32bit PCI busmaster DMA\n");
453 return i;
454 }
455
456 pci_set_master(pci_dev);
457
458 net_dev = alloc_etherdev(sizeof(struct sis900_private));
459 if (!net_dev)
460 return -ENOMEM;
461 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
462
463
464 ret = pci_request_regions(pci_dev, "sis900");
465 if (ret)
466 goto err_out;
467
468
469 ioaddr = pci_iomap(pci_dev, 0, 0);
470 if (!ioaddr) {
471 ret = -ENOMEM;
472 goto err_out_cleardev;
473 }
474
475 sis_priv = netdev_priv(net_dev);
476 sis_priv->ioaddr = ioaddr;
477 sis_priv->pci_dev = pci_dev;
478 spin_lock_init(&sis_priv->lock);
479
480 sis_priv->eeprom_size = 24;
481
482 pci_set_drvdata(pci_dev, net_dev);
483
484 ring_space = pci_alloc_consistent(pci_dev, TX_TOTAL_SIZE, &ring_dma);
485 if (!ring_space) {
486 ret = -ENOMEM;
487 goto err_out_unmap;
488 }
489 sis_priv->tx_ring = ring_space;
490 sis_priv->tx_ring_dma = ring_dma;
491
492 ring_space = pci_alloc_consistent(pci_dev, RX_TOTAL_SIZE, &ring_dma);
493 if (!ring_space) {
494 ret = -ENOMEM;
495 goto err_unmap_tx;
496 }
497 sis_priv->rx_ring = ring_space;
498 sis_priv->rx_ring_dma = ring_dma;
499
500
501 net_dev->netdev_ops = &sis900_netdev_ops;
502 net_dev->watchdog_timeo = TX_TIMEOUT;
503 net_dev->ethtool_ops = &sis900_ethtool_ops;
504
505 if (sis900_debug > 0)
506 sis_priv->msg_enable = sis900_debug;
507 else
508 sis_priv->msg_enable = SIS900_DEF_MSG;
509
510 sis_priv->mii_info.dev = net_dev;
511 sis_priv->mii_info.mdio_read = mdio_read;
512 sis_priv->mii_info.mdio_write = mdio_write;
513 sis_priv->mii_info.phy_id_mask = 0x1f;
514 sis_priv->mii_info.reg_num_mask = 0x1f;
515
516
517 sis_priv->chipset_rev = pci_dev->revision;
518 if(netif_msg_probe(sis_priv))
519 printk(KERN_DEBUG "%s: detected revision %2.2x, "
520 "trying to get MAC address...\n",
521 dev_name, sis_priv->chipset_rev);
522
523 ret = 0;
524 if (sis_priv->chipset_rev == SIS630E_900_REV)
525 ret = sis630e_get_mac_addr(pci_dev, net_dev);
526 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
527 ret = sis635_get_mac_addr(pci_dev, net_dev);
528 else if (sis_priv->chipset_rev == SIS96x_900_REV)
529 ret = sis96x_get_mac_addr(pci_dev, net_dev);
530 else
531 ret = sis900_get_mac_addr(pci_dev, net_dev);
532
533 if (!ret || !is_valid_ether_addr(net_dev->dev_addr)) {
534 eth_hw_addr_random(net_dev);
535 printk(KERN_WARNING "%s: Unreadable or invalid MAC address,"
536 "using random generated one\n", dev_name);
537 }
538
539
540 if (sis_priv->chipset_rev == SIS630ET_900_REV)
541 sw32(cr, ACCESSMODE | sr32(cr));
542
543
544 if (sis900_mii_probe(net_dev) == 0) {
545 printk(KERN_WARNING "%s: Error probing MII device.\n",
546 dev_name);
547 ret = -ENODEV;
548 goto err_unmap_rx;
549 }
550
551
552 dev = pci_get_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630, NULL);
553 if (dev) {
554 sis_priv->host_bridge_rev = dev->revision;
555 pci_dev_put(dev);
556 }
557
558 ret = register_netdev(net_dev);
559 if (ret)
560 goto err_unmap_rx;
561
562
563 printk(KERN_INFO "%s: %s at 0x%p, IRQ %d, %pM\n",
564 net_dev->name, card_name, ioaddr, pci_dev->irq,
565 net_dev->dev_addr);
566
567
568 ret = (sr32(CFGPMC) & PMESP) >> 27;
569 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
570 printk(KERN_INFO "%s: Wake on LAN only available from suspend to RAM.", net_dev->name);
571
572 return 0;
573
574 err_unmap_rx:
575 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
576 sis_priv->rx_ring_dma);
577 err_unmap_tx:
578 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
579 sis_priv->tx_ring_dma);
580 err_out_unmap:
581 pci_iounmap(pci_dev, ioaddr);
582 err_out_cleardev:
583 pci_release_regions(pci_dev);
584 err_out:
585 free_netdev(net_dev);
586 return ret;
587 }
588
589
590
591
592
593
594
595
596
597
598 static int sis900_mii_probe(struct net_device *net_dev)
599 {
600 struct sis900_private *sis_priv = netdev_priv(net_dev);
601 const char *dev_name = pci_name(sis_priv->pci_dev);
602 u16 poll_bit = MII_STAT_LINK, status = 0;
603 unsigned long timeout = jiffies + 5 * HZ;
604 int phy_addr;
605
606 sis_priv->mii = NULL;
607
608
609 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
610 struct mii_phy * mii_phy = NULL;
611 u16 mii_status;
612 int i;
613
614 mii_phy = NULL;
615 for(i = 0; i < 2; i++)
616 mii_status = mdio_read(net_dev, phy_addr, MII_STATUS);
617
618 if (mii_status == 0xffff || mii_status == 0x0000) {
619 if (netif_msg_probe(sis_priv))
620 printk(KERN_DEBUG "%s: MII at address %d"
621 " not accessible\n",
622 dev_name, phy_addr);
623 continue;
624 }
625
626 if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) == NULL) {
627 mii_phy = sis_priv->first_mii;
628 while (mii_phy) {
629 struct mii_phy *phy;
630 phy = mii_phy;
631 mii_phy = mii_phy->next;
632 kfree(phy);
633 }
634 return 0;
635 }
636
637 mii_phy->phy_id0 = mdio_read(net_dev, phy_addr, MII_PHY_ID0);
638 mii_phy->phy_id1 = mdio_read(net_dev, phy_addr, MII_PHY_ID1);
639 mii_phy->phy_addr = phy_addr;
640 mii_phy->status = mii_status;
641 mii_phy->next = sis_priv->mii;
642 sis_priv->mii = mii_phy;
643 sis_priv->first_mii = mii_phy;
644
645 for (i = 0; mii_chip_table[i].phy_id1; i++)
646 if ((mii_phy->phy_id0 == mii_chip_table[i].phy_id0 ) &&
647 ((mii_phy->phy_id1 & 0xFFF0) == mii_chip_table[i].phy_id1)){
648 mii_phy->phy_types = mii_chip_table[i].phy_types;
649 if (mii_chip_table[i].phy_types == MIX)
650 mii_phy->phy_types =
651 (mii_status & (MII_STAT_CAN_TX_FDX | MII_STAT_CAN_TX)) ? LAN : HOME;
652 printk(KERN_INFO "%s: %s transceiver found "
653 "at address %d.\n",
654 dev_name,
655 mii_chip_table[i].name,
656 phy_addr);
657 break;
658 }
659
660 if( !mii_chip_table[i].phy_id1 ) {
661 printk(KERN_INFO "%s: Unknown PHY transceiver found at address %d.\n",
662 dev_name, phy_addr);
663 mii_phy->phy_types = UNKNOWN;
664 }
665 }
666
667 if (sis_priv->mii == NULL) {
668 printk(KERN_INFO "%s: No MII transceivers found!\n", dev_name);
669 return 0;
670 }
671
672
673 sis_priv->mii = NULL;
674 sis900_default_phy( net_dev );
675
676
677 if ((sis_priv->mii->phy_id0 == 0x001D) &&
678 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
679 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
680
681
682 if ((sis_priv->mii->phy_id0 == 0x0015) &&
683 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
684 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
685
686 if(status & MII_STAT_LINK){
687 while (poll_bit) {
688 yield();
689
690 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
691 if (time_after_eq(jiffies, timeout)) {
692 printk(KERN_WARNING "%s: reset phy and link down now\n",
693 dev_name);
694 return -ETIME;
695 }
696 }
697 }
698
699 if (sis_priv->chipset_rev == SIS630E_900_REV) {
700
701 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
702 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
703 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
704 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
705
706 }
707
708 if (sis_priv->mii->status & MII_STAT_LINK)
709 netif_carrier_on(net_dev);
710 else
711 netif_carrier_off(net_dev);
712
713 return 1;
714 }
715
716
717
718
719
720
721
722
723
724
725 static u16 sis900_default_phy(struct net_device * net_dev)
726 {
727 struct sis900_private *sis_priv = netdev_priv(net_dev);
728 struct mii_phy *phy = NULL, *phy_home = NULL,
729 *default_phy = NULL, *phy_lan = NULL;
730 u16 status;
731
732 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
733 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
734 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
735
736
737 if ((status & MII_STAT_LINK) && !default_phy &&
738 (phy->phy_types != UNKNOWN)) {
739 default_phy = phy;
740 } else {
741 status = mdio_read(net_dev, phy->phy_addr, MII_CONTROL);
742 mdio_write(net_dev, phy->phy_addr, MII_CONTROL,
743 status | MII_CNTL_AUTO | MII_CNTL_ISOLATE);
744 if (phy->phy_types == HOME)
745 phy_home = phy;
746 else if(phy->phy_types == LAN)
747 phy_lan = phy;
748 }
749 }
750
751 if (!default_phy && phy_home)
752 default_phy = phy_home;
753 else if (!default_phy && phy_lan)
754 default_phy = phy_lan;
755 else if (!default_phy)
756 default_phy = sis_priv->first_mii;
757
758 if (sis_priv->mii != default_phy) {
759 sis_priv->mii = default_phy;
760 sis_priv->cur_phy = default_phy->phy_addr;
761 printk(KERN_INFO "%s: Using transceiver found at address %d as default\n",
762 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
763 }
764
765 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
766
767 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
768 status &= (~MII_CNTL_ISOLATE);
769
770 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
771 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
772 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
773
774 return status;
775 }
776
777
778
779
780
781
782
783
784
785
786
787 static void sis900_set_capability(struct net_device *net_dev, struct mii_phy *phy)
788 {
789 u16 cap;
790 u16 status;
791
792 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
793 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
794
795 cap = MII_NWAY_CSMA_CD |
796 ((phy->status & MII_STAT_CAN_TX_FDX)? MII_NWAY_TX_FDX:0) |
797 ((phy->status & MII_STAT_CAN_TX) ? MII_NWAY_TX:0) |
798 ((phy->status & MII_STAT_CAN_T_FDX) ? MII_NWAY_T_FDX:0)|
799 ((phy->status & MII_STAT_CAN_T) ? MII_NWAY_T:0);
800
801 mdio_write(net_dev, phy->phy_addr, MII_ANADV, cap);
802 }
803
804
805
806 #define eeprom_delay() sr32(mear)
807
808
809
810
811
812
813
814
815
816
817 static u16 read_eeprom(void __iomem *ioaddr, int location)
818 {
819 u32 read_cmd = location | EEread;
820 int i;
821 u16 retval = 0;
822
823 sw32(mear, 0);
824 eeprom_delay();
825 sw32(mear, EECS);
826 eeprom_delay();
827
828
829 for (i = 8; i >= 0; i--) {
830 u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
831
832 sw32(mear, dataval);
833 eeprom_delay();
834 sw32(mear, dataval | EECLK);
835 eeprom_delay();
836 }
837 sw32(mear, EECS);
838 eeprom_delay();
839
840
841 for (i = 16; i > 0; i--) {
842 sw32(mear, EECS);
843 eeprom_delay();
844 sw32(mear, EECS | EECLK);
845 eeprom_delay();
846 retval = (retval << 1) | ((sr32(mear) & EEDO) ? 1 : 0);
847 eeprom_delay();
848 }
849
850
851 sw32(mear, 0);
852 eeprom_delay();
853
854 return retval;
855 }
856
857
858
859
860 #define mdio_delay() sr32(mear)
861
862 static void mdio_idle(struct sis900_private *sp)
863 {
864 void __iomem *ioaddr = sp->ioaddr;
865
866 sw32(mear, MDIO | MDDIR);
867 mdio_delay();
868 sw32(mear, MDIO | MDDIR | MDC);
869 }
870
871
872 static void mdio_reset(struct sis900_private *sp)
873 {
874 void __iomem *ioaddr = sp->ioaddr;
875 int i;
876
877 for (i = 31; i >= 0; i--) {
878 sw32(mear, MDDIR | MDIO);
879 mdio_delay();
880 sw32(mear, MDDIR | MDIO | MDC);
881 mdio_delay();
882 }
883 }
884
885
886
887
888
889
890
891
892
893
894
895
896 static int mdio_read(struct net_device *net_dev, int phy_id, int location)
897 {
898 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
899 struct sis900_private *sp = netdev_priv(net_dev);
900 void __iomem *ioaddr = sp->ioaddr;
901 u16 retval = 0;
902 int i;
903
904 mdio_reset(sp);
905 mdio_idle(sp);
906
907 for (i = 15; i >= 0; i--) {
908 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
909
910 sw32(mear, dataval);
911 mdio_delay();
912 sw32(mear, dataval | MDC);
913 mdio_delay();
914 }
915
916
917 for (i = 16; i > 0; i--) {
918 sw32(mear, 0);
919 mdio_delay();
920 retval = (retval << 1) | ((sr32(mear) & MDIO) ? 1 : 0);
921 sw32(mear, MDC);
922 mdio_delay();
923 }
924 sw32(mear, 0x00);
925
926 return retval;
927 }
928
929
930
931
932
933
934
935
936
937
938
939
940
941 static void mdio_write(struct net_device *net_dev, int phy_id, int location,
942 int value)
943 {
944 int mii_cmd = MIIwrite|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
945 struct sis900_private *sp = netdev_priv(net_dev);
946 void __iomem *ioaddr = sp->ioaddr;
947 int i;
948
949 mdio_reset(sp);
950 mdio_idle(sp);
951
952
953 for (i = 15; i >= 0; i--) {
954 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
955
956 sw8(mear, dataval);
957 mdio_delay();
958 sw8(mear, dataval | MDC);
959 mdio_delay();
960 }
961 mdio_delay();
962
963
964 for (i = 15; i >= 0; i--) {
965 int dataval = (value & (1 << i)) ? MDDIR | MDIO : MDDIR;
966
967 sw32(mear, dataval);
968 mdio_delay();
969 sw32(mear, dataval | MDC);
970 mdio_delay();
971 }
972 mdio_delay();
973
974
975 for (i = 2; i > 0; i--) {
976 sw8(mear, 0);
977 mdio_delay();
978 sw8(mear, MDC);
979 mdio_delay();
980 }
981 sw32(mear, 0x00);
982 }
983
984
985
986
987
988
989
990
991
992
993
994
995 static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr)
996 {
997 int i;
998 u16 status;
999
1000 for (i = 0; i < 2; i++)
1001 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1002
1003 mdio_write( net_dev, phy_addr, MII_CONTROL, MII_CNTL_RESET );
1004
1005 return status;
1006 }
1007
1008 #ifdef CONFIG_NET_POLL_CONTROLLER
1009
1010
1011
1012
1013
1014 static void sis900_poll(struct net_device *dev)
1015 {
1016 struct sis900_private *sp = netdev_priv(dev);
1017 const int irq = sp->pci_dev->irq;
1018
1019 disable_irq(irq);
1020 sis900_interrupt(irq, dev);
1021 enable_irq(irq);
1022 }
1023 #endif
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033 static int
1034 sis900_open(struct net_device *net_dev)
1035 {
1036 struct sis900_private *sis_priv = netdev_priv(net_dev);
1037 void __iomem *ioaddr = sis_priv->ioaddr;
1038 int ret;
1039
1040
1041 sis900_reset(net_dev);
1042
1043
1044 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1045
1046 ret = request_irq(sis_priv->pci_dev->irq, sis900_interrupt, IRQF_SHARED,
1047 net_dev->name, net_dev);
1048 if (ret)
1049 return ret;
1050
1051 sis900_init_rxfilter(net_dev);
1052
1053 sis900_init_tx_ring(net_dev);
1054 sis900_init_rx_ring(net_dev);
1055
1056 set_rx_mode(net_dev);
1057
1058 netif_start_queue(net_dev);
1059
1060
1061 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1062
1063
1064 sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);
1065 sw32(cr, RxENA | sr32(cr));
1066 sw32(ier, IE);
1067
1068 sis900_check_mode(net_dev, sis_priv->mii);
1069
1070
1071
1072 timer_setup(&sis_priv->timer, sis900_timer, 0);
1073 sis_priv->timer.expires = jiffies + HZ;
1074 add_timer(&sis_priv->timer);
1075
1076 return 0;
1077 }
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087 static void
1088 sis900_init_rxfilter (struct net_device * net_dev)
1089 {
1090 struct sis900_private *sis_priv = netdev_priv(net_dev);
1091 void __iomem *ioaddr = sis_priv->ioaddr;
1092 u32 rfcrSave;
1093 u32 i;
1094
1095 rfcrSave = sr32(rfcr);
1096
1097
1098 sw32(rfcr, rfcrSave & ~RFEN);
1099
1100
1101 for (i = 0 ; i < 3 ; i++) {
1102 u32 w = (u32) *((u16 *)(net_dev->dev_addr)+i);
1103
1104 sw32(rfcr, i << RFADDR_shift);
1105 sw32(rfdr, w);
1106
1107 if (netif_msg_hw(sis_priv)) {
1108 printk(KERN_DEBUG "%s: Receive Filter Address[%d]=%x\n",
1109 net_dev->name, i, sr32(rfdr));
1110 }
1111 }
1112
1113
1114 sw32(rfcr, rfcrSave | RFEN);
1115 }
1116
1117
1118
1119
1120
1121
1122
1123
1124 static void
1125 sis900_init_tx_ring(struct net_device *net_dev)
1126 {
1127 struct sis900_private *sis_priv = netdev_priv(net_dev);
1128 void __iomem *ioaddr = sis_priv->ioaddr;
1129 int i;
1130
1131 sis_priv->tx_full = 0;
1132 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1133
1134 for (i = 0; i < NUM_TX_DESC; i++) {
1135 sis_priv->tx_skbuff[i] = NULL;
1136
1137 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1138 ((i+1)%NUM_TX_DESC)*sizeof(BufferDesc);
1139 sis_priv->tx_ring[i].cmdsts = 0;
1140 sis_priv->tx_ring[i].bufptr = 0;
1141 }
1142
1143
1144 sw32(txdp, sis_priv->tx_ring_dma);
1145 if (netif_msg_hw(sis_priv))
1146 printk(KERN_DEBUG "%s: TX descriptor register loaded with: %8.8x\n",
1147 net_dev->name, sr32(txdp));
1148 }
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158 static void
1159 sis900_init_rx_ring(struct net_device *net_dev)
1160 {
1161 struct sis900_private *sis_priv = netdev_priv(net_dev);
1162 void __iomem *ioaddr = sis_priv->ioaddr;
1163 int i;
1164
1165 sis_priv->cur_rx = 0;
1166 sis_priv->dirty_rx = 0;
1167
1168
1169 for (i = 0; i < NUM_RX_DESC; i++) {
1170 sis_priv->rx_skbuff[i] = NULL;
1171
1172 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1173 ((i+1)%NUM_RX_DESC)*sizeof(BufferDesc);
1174 sis_priv->rx_ring[i].cmdsts = 0;
1175 sis_priv->rx_ring[i].bufptr = 0;
1176 }
1177
1178
1179 for (i = 0; i < NUM_RX_DESC; i++) {
1180 struct sk_buff *skb;
1181
1182 if ((skb = netdev_alloc_skb(net_dev, RX_BUF_SIZE)) == NULL) {
1183
1184
1185
1186
1187 break;
1188 }
1189 sis_priv->rx_skbuff[i] = skb;
1190 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1191 sis_priv->rx_ring[i].bufptr = pci_map_single(sis_priv->pci_dev,
1192 skb->data, RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1193 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1194 sis_priv->rx_ring[i].bufptr))) {
1195 dev_kfree_skb(skb);
1196 sis_priv->rx_skbuff[i] = NULL;
1197 break;
1198 }
1199 }
1200 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1201
1202
1203 sw32(rxdp, sis_priv->rx_ring_dma);
1204 if (netif_msg_hw(sis_priv))
1205 printk(KERN_DEBUG "%s: RX descriptor register loaded with: %8.8x\n",
1206 net_dev->name, sr32(rxdp));
1207 }
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236 static void sis630_set_eq(struct net_device *net_dev, u8 revision)
1237 {
1238 struct sis900_private *sis_priv = netdev_priv(net_dev);
1239 u16 reg14h, eq_value=0, max_value=0, min_value=0;
1240 int i, maxcount=10;
1241
1242 if ( !(revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1243 revision == SIS630A_900_REV || revision == SIS630ET_900_REV) )
1244 return;
1245
1246 if (netif_carrier_ok(net_dev)) {
1247 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1248 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1249 (0x2200 | reg14h) & 0xBFFF);
1250 for (i=0; i < maxcount; i++) {
1251 eq_value = (0x00F8 & mdio_read(net_dev,
1252 sis_priv->cur_phy, MII_RESV)) >> 3;
1253 if (i == 0)
1254 max_value=min_value=eq_value;
1255 max_value = (eq_value > max_value) ?
1256 eq_value : max_value;
1257 min_value = (eq_value < min_value) ?
1258 eq_value : min_value;
1259 }
1260
1261 if (revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1262 revision == SIS630ET_900_REV) {
1263 if (max_value < 5)
1264 eq_value = max_value;
1265 else if (max_value >= 5 && max_value < 15)
1266 eq_value = (max_value == min_value) ?
1267 max_value+2 : max_value+1;
1268 else if (max_value >= 15)
1269 eq_value=(max_value == min_value) ?
1270 max_value+6 : max_value+5;
1271 }
1272
1273 if (revision == SIS630A_900_REV &&
1274 (sis_priv->host_bridge_rev == SIS630B0 ||
1275 sis_priv->host_bridge_rev == SIS630B1)) {
1276 if (max_value == 0)
1277 eq_value = 3;
1278 else
1279 eq_value = (max_value + min_value + 1)/2;
1280 }
1281
1282 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1283 reg14h = (reg14h & 0xFF07) | ((eq_value << 3) & 0x00F8);
1284 reg14h = (reg14h | 0x6000) & 0xFDFF;
1285 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1286 } else {
1287 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1288 if (revision == SIS630A_900_REV &&
1289 (sis_priv->host_bridge_rev == SIS630B0 ||
1290 sis_priv->host_bridge_rev == SIS630B1))
1291 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1292 (reg14h | 0x2200) & 0xBFFF);
1293 else
1294 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1295 (reg14h | 0x2000) & 0xBFFF);
1296 }
1297 }
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307 static void sis900_timer(struct timer_list *t)
1308 {
1309 struct sis900_private *sis_priv = from_timer(sis_priv, t, timer);
1310 struct net_device *net_dev = sis_priv->mii_info.dev;
1311 struct mii_phy *mii_phy = sis_priv->mii;
1312 static const int next_tick = 5*HZ;
1313 int speed = 0, duplex = 0;
1314 u16 status;
1315
1316 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1317 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1318
1319
1320 if (!netif_carrier_ok(net_dev)) {
1321 LookForLink:
1322
1323 status = sis900_default_phy(net_dev);
1324 mii_phy = sis_priv->mii;
1325
1326 if (status & MII_STAT_LINK) {
1327 WARN_ON(!(status & MII_STAT_AUTO_DONE));
1328
1329 sis900_read_mode(net_dev, &speed, &duplex);
1330 if (duplex) {
1331 sis900_set_mode(sis_priv, speed, duplex);
1332 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1333 netif_carrier_on(net_dev);
1334 }
1335 }
1336 } else {
1337
1338 if (!(status & MII_STAT_LINK)){
1339 netif_carrier_off(net_dev);
1340 if(netif_msg_link(sis_priv))
1341 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1342
1343
1344 if ((mii_phy->phy_id0 == 0x001D) &&
1345 ((mii_phy->phy_id1 & 0xFFF0) == 0x8000))
1346 sis900_reset_phy(net_dev, sis_priv->cur_phy);
1347
1348 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1349
1350 goto LookForLink;
1351 }
1352 }
1353
1354 sis_priv->timer.expires = jiffies + next_tick;
1355 add_timer(&sis_priv->timer);
1356 }
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370 static void sis900_check_mode(struct net_device *net_dev, struct mii_phy *mii_phy)
1371 {
1372 struct sis900_private *sis_priv = netdev_priv(net_dev);
1373 void __iomem *ioaddr = sis_priv->ioaddr;
1374 int speed, duplex;
1375
1376 if (mii_phy->phy_types == LAN) {
1377 sw32(cfg, ~EXD & sr32(cfg));
1378 sis900_set_capability(net_dev , mii_phy);
1379 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1380 } else {
1381 sw32(cfg, EXD | sr32(cfg));
1382 speed = HW_SPEED_HOME;
1383 duplex = FDX_CAPABLE_HALF_SELECTED;
1384 sis900_set_mode(sis_priv, speed, duplex);
1385 sis_priv->autong_complete = 1;
1386 }
1387 }
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402 static void sis900_set_mode(struct sis900_private *sp, int speed, int duplex)
1403 {
1404 void __iomem *ioaddr = sp->ioaddr;
1405 u32 tx_flags = 0, rx_flags = 0;
1406
1407 if (sr32( cfg) & EDB_MASTER_EN) {
1408 tx_flags = TxATP | (DMA_BURST_64 << TxMXDMA_shift) |
1409 (TX_FILL_THRESH << TxFILLT_shift);
1410 rx_flags = DMA_BURST_64 << RxMXDMA_shift;
1411 } else {
1412 tx_flags = TxATP | (DMA_BURST_512 << TxMXDMA_shift) |
1413 (TX_FILL_THRESH << TxFILLT_shift);
1414 rx_flags = DMA_BURST_512 << RxMXDMA_shift;
1415 }
1416
1417 if (speed == HW_SPEED_HOME || speed == HW_SPEED_10_MBPS) {
1418 rx_flags |= (RxDRNT_10 << RxDRNT_shift);
1419 tx_flags |= (TxDRNT_10 << TxDRNT_shift);
1420 } else {
1421 rx_flags |= (RxDRNT_100 << RxDRNT_shift);
1422 tx_flags |= (TxDRNT_100 << TxDRNT_shift);
1423 }
1424
1425 if (duplex == FDX_CAPABLE_FULL_SELECTED) {
1426 tx_flags |= (TxCSI | TxHBI);
1427 rx_flags |= RxATX;
1428 }
1429
1430 #if IS_ENABLED(CONFIG_VLAN_8021Q)
1431
1432 rx_flags |= RxAJAB;
1433 #endif
1434
1435 sw32(txcfg, tx_flags);
1436 sw32(rxcfg, rx_flags);
1437 }
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450 static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr)
1451 {
1452 struct sis900_private *sis_priv = netdev_priv(net_dev);
1453 int i = 0;
1454 u32 status;
1455
1456 for (i = 0; i < 2; i++)
1457 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1458
1459 if (!(status & MII_STAT_LINK)){
1460 if(netif_msg_link(sis_priv))
1461 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1462 sis_priv->autong_complete = 1;
1463 netif_carrier_off(net_dev);
1464 return;
1465 }
1466
1467
1468 mdio_write(net_dev, phy_addr, MII_CONTROL,
1469 MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
1470 sis_priv->autong_complete = 0;
1471 }
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485 static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex)
1486 {
1487 struct sis900_private *sis_priv = netdev_priv(net_dev);
1488 struct mii_phy *phy = sis_priv->mii;
1489 int phy_addr = sis_priv->cur_phy;
1490 u32 status;
1491 u16 autoadv, autorec;
1492 int i;
1493
1494 for (i = 0; i < 2; i++)
1495 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1496
1497 if (!(status & MII_STAT_LINK))
1498 return;
1499
1500
1501 autoadv = mdio_read(net_dev, phy_addr, MII_ANADV);
1502 autorec = mdio_read(net_dev, phy_addr, MII_ANLPAR);
1503 status = autoadv & autorec;
1504
1505 *speed = HW_SPEED_10_MBPS;
1506 *duplex = FDX_CAPABLE_HALF_SELECTED;
1507
1508 if (status & (MII_NWAY_TX | MII_NWAY_TX_FDX))
1509 *speed = HW_SPEED_100_MBPS;
1510 if (status & ( MII_NWAY_TX_FDX | MII_NWAY_T_FDX))
1511 *duplex = FDX_CAPABLE_FULL_SELECTED;
1512
1513 sis_priv->autong_complete = 1;
1514
1515
1516 if ((phy->phy_id0 == 0x0000) && ((phy->phy_id1 & 0xFFF0) == 0x8200)) {
1517 if (mdio_read(net_dev, phy_addr, MII_CONTROL) & MII_CNTL_FDX)
1518 *duplex = FDX_CAPABLE_FULL_SELECTED;
1519 if (mdio_read(net_dev, phy_addr, 0x0019) & 0x01)
1520 *speed = HW_SPEED_100_MBPS;
1521 }
1522
1523 if(netif_msg_link(sis_priv))
1524 printk(KERN_INFO "%s: Media Link On %s %s-duplex\n",
1525 net_dev->name,
1526 *speed == HW_SPEED_100_MBPS ?
1527 "100mbps" : "10mbps",
1528 *duplex == FDX_CAPABLE_FULL_SELECTED ?
1529 "full" : "half");
1530 }
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540 static void sis900_tx_timeout(struct net_device *net_dev)
1541 {
1542 struct sis900_private *sis_priv = netdev_priv(net_dev);
1543 void __iomem *ioaddr = sis_priv->ioaddr;
1544 unsigned long flags;
1545 int i;
1546
1547 if (netif_msg_tx_err(sis_priv)) {
1548 printk(KERN_INFO "%s: Transmit timeout, status %8.8x %8.8x\n",
1549 net_dev->name, sr32(cr), sr32(isr));
1550 }
1551
1552
1553 sw32(imr, 0x0000);
1554
1555
1556 spin_lock_irqsave(&sis_priv->lock, flags);
1557
1558
1559 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1560 for (i = 0; i < NUM_TX_DESC; i++) {
1561 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1562
1563 if (skb) {
1564 pci_unmap_single(sis_priv->pci_dev,
1565 sis_priv->tx_ring[i].bufptr, skb->len,
1566 PCI_DMA_TODEVICE);
1567 dev_kfree_skb_irq(skb);
1568 sis_priv->tx_skbuff[i] = NULL;
1569 sis_priv->tx_ring[i].cmdsts = 0;
1570 sis_priv->tx_ring[i].bufptr = 0;
1571 net_dev->stats.tx_dropped++;
1572 }
1573 }
1574 sis_priv->tx_full = 0;
1575 netif_wake_queue(net_dev);
1576
1577 spin_unlock_irqrestore(&sis_priv->lock, flags);
1578
1579 netif_trans_update(net_dev);
1580
1581
1582 sw32(txdp, sis_priv->tx_ring_dma);
1583
1584
1585 sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);
1586 }
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598 static netdev_tx_t
1599 sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
1600 {
1601 struct sis900_private *sis_priv = netdev_priv(net_dev);
1602 void __iomem *ioaddr = sis_priv->ioaddr;
1603 unsigned int entry;
1604 unsigned long flags;
1605 unsigned int index_cur_tx, index_dirty_tx;
1606 unsigned int count_dirty_tx;
1607
1608 spin_lock_irqsave(&sis_priv->lock, flags);
1609
1610
1611 entry = sis_priv->cur_tx % NUM_TX_DESC;
1612 sis_priv->tx_skbuff[entry] = skb;
1613
1614
1615 sis_priv->tx_ring[entry].bufptr = pci_map_single(sis_priv->pci_dev,
1616 skb->data, skb->len, PCI_DMA_TODEVICE);
1617 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1618 sis_priv->tx_ring[entry].bufptr))) {
1619 dev_kfree_skb_any(skb);
1620 sis_priv->tx_skbuff[entry] = NULL;
1621 net_dev->stats.tx_dropped++;
1622 spin_unlock_irqrestore(&sis_priv->lock, flags);
1623 return NETDEV_TX_OK;
1624 }
1625 sis_priv->tx_ring[entry].cmdsts = (OWN | INTR | skb->len);
1626 sw32(cr, TxENA | sr32(cr));
1627
1628 sis_priv->cur_tx ++;
1629 index_cur_tx = sis_priv->cur_tx;
1630 index_dirty_tx = sis_priv->dirty_tx;
1631
1632 for (count_dirty_tx = 0; index_cur_tx != index_dirty_tx; index_dirty_tx++)
1633 count_dirty_tx ++;
1634
1635 if (index_cur_tx == index_dirty_tx) {
1636
1637 sis_priv->tx_full = 1;
1638 netif_stop_queue(net_dev);
1639 } else if (count_dirty_tx < NUM_TX_DESC) {
1640
1641 netif_start_queue(net_dev);
1642 } else {
1643
1644 sis_priv->tx_full = 1;
1645 netif_stop_queue(net_dev);
1646 }
1647
1648 spin_unlock_irqrestore(&sis_priv->lock, flags);
1649
1650 if (netif_msg_tx_queued(sis_priv))
1651 printk(KERN_DEBUG "%s: Queued Tx packet at %p size %d "
1652 "to slot %d.\n",
1653 net_dev->name, skb->data, (int)skb->len, entry);
1654
1655 return NETDEV_TX_OK;
1656 }
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667 static irqreturn_t sis900_interrupt(int irq, void *dev_instance)
1668 {
1669 struct net_device *net_dev = dev_instance;
1670 struct sis900_private *sis_priv = netdev_priv(net_dev);
1671 int boguscnt = max_interrupt_work;
1672 void __iomem *ioaddr = sis_priv->ioaddr;
1673 u32 status;
1674 unsigned int handled = 0;
1675
1676 spin_lock (&sis_priv->lock);
1677
1678 do {
1679 status = sr32(isr);
1680
1681 if ((status & (HIBERR|TxURN|TxERR|TxDESC|RxORN|RxERR|RxOK)) == 0)
1682
1683 break;
1684 handled = 1;
1685
1686
1687 if (status & (RxORN | RxERR | RxOK))
1688
1689 sis900_rx(net_dev);
1690
1691 if (status & (TxURN | TxERR | TxDESC))
1692
1693 sis900_finish_xmit(net_dev);
1694
1695
1696 if (status & HIBERR) {
1697 if(netif_msg_intr(sis_priv))
1698 printk(KERN_INFO "%s: Abnormal interrupt, "
1699 "status %#8.8x.\n", net_dev->name, status);
1700 break;
1701 }
1702 if (--boguscnt < 0) {
1703 if(netif_msg_intr(sis_priv))
1704 printk(KERN_INFO "%s: Too much work at interrupt, "
1705 "interrupt status = %#8.8x.\n",
1706 net_dev->name, status);
1707 break;
1708 }
1709 } while (1);
1710
1711 if(netif_msg_intr(sis_priv))
1712 printk(KERN_DEBUG "%s: exiting interrupt, "
1713 "interrupt status = %#8.8x\n",
1714 net_dev->name, sr32(isr));
1715
1716 spin_unlock (&sis_priv->lock);
1717 return IRQ_RETVAL(handled);
1718 }
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730 static int sis900_rx(struct net_device *net_dev)
1731 {
1732 struct sis900_private *sis_priv = netdev_priv(net_dev);
1733 void __iomem *ioaddr = sis_priv->ioaddr;
1734 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1735 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
1736 int rx_work_limit;
1737
1738 if (netif_msg_rx_status(sis_priv))
1739 printk(KERN_DEBUG "sis900_rx, cur_rx:%4.4d, dirty_rx:%4.4d "
1740 "status:0x%8.8x\n",
1741 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
1742 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1743
1744 while (rx_status & OWN) {
1745 unsigned int rx_size;
1746 unsigned int data_size;
1747
1748 if (--rx_work_limit < 0)
1749 break;
1750
1751 data_size = rx_status & DSIZE;
1752 rx_size = data_size - CRC_SIZE;
1753
1754 #if IS_ENABLED(CONFIG_VLAN_8021Q)
1755
1756 if ((rx_status & TOOLONG) && data_size <= MAX_FRAME_SIZE)
1757 rx_status &= (~ ((unsigned int)TOOLONG));
1758 #endif
1759
1760 if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) {
1761
1762 if (netif_msg_rx_err(sis_priv))
1763 printk(KERN_DEBUG "%s: Corrupted packet "
1764 "received, buffer status = 0x%8.8x/%d.\n",
1765 net_dev->name, rx_status, data_size);
1766 net_dev->stats.rx_errors++;
1767 if (rx_status & OVERRUN)
1768 net_dev->stats.rx_over_errors++;
1769 if (rx_status & (TOOLONG|RUNT))
1770 net_dev->stats.rx_length_errors++;
1771 if (rx_status & (RXISERR | FAERR))
1772 net_dev->stats.rx_frame_errors++;
1773 if (rx_status & CRCERR)
1774 net_dev->stats.rx_crc_errors++;
1775
1776 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1777 } else {
1778 struct sk_buff * skb;
1779 struct sk_buff * rx_skb;
1780
1781 pci_unmap_single(sis_priv->pci_dev,
1782 sis_priv->rx_ring[entry].bufptr, RX_BUF_SIZE,
1783 PCI_DMA_FROMDEVICE);
1784
1785
1786
1787 if ((skb = netdev_alloc_skb(net_dev, RX_BUF_SIZE)) == NULL) {
1788
1789
1790
1791
1792
1793
1794 skb = sis_priv->rx_skbuff[entry];
1795 net_dev->stats.rx_dropped++;
1796 goto refill_rx_ring;
1797 }
1798
1799
1800
1801
1802 if (sis_priv->rx_skbuff[entry] == NULL) {
1803 if (netif_msg_rx_err(sis_priv))
1804 printk(KERN_WARNING "%s: NULL pointer "
1805 "encountered in Rx ring\n"
1806 "cur_rx:%4.4d, dirty_rx:%4.4d\n",
1807 net_dev->name, sis_priv->cur_rx,
1808 sis_priv->dirty_rx);
1809 dev_kfree_skb(skb);
1810 break;
1811 }
1812
1813
1814 rx_skb = sis_priv->rx_skbuff[entry];
1815 skb_put(rx_skb, rx_size);
1816 rx_skb->protocol = eth_type_trans(rx_skb, net_dev);
1817 netif_rx(rx_skb);
1818
1819
1820 if ((rx_status & BCAST) == MCAST)
1821 net_dev->stats.multicast++;
1822 net_dev->stats.rx_bytes += rx_size;
1823 net_dev->stats.rx_packets++;
1824 sis_priv->dirty_rx++;
1825 refill_rx_ring:
1826 sis_priv->rx_skbuff[entry] = skb;
1827 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1828 sis_priv->rx_ring[entry].bufptr =
1829 pci_map_single(sis_priv->pci_dev, skb->data,
1830 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1831 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1832 sis_priv->rx_ring[entry].bufptr))) {
1833 dev_kfree_skb_irq(skb);
1834 sis_priv->rx_skbuff[entry] = NULL;
1835 break;
1836 }
1837 }
1838 sis_priv->cur_rx++;
1839 entry = sis_priv->cur_rx % NUM_RX_DESC;
1840 rx_status = sis_priv->rx_ring[entry].cmdsts;
1841 }
1842
1843
1844
1845 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1846 struct sk_buff *skb;
1847
1848 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1849
1850 if (sis_priv->rx_skbuff[entry] == NULL) {
1851 skb = netdev_alloc_skb(net_dev, RX_BUF_SIZE);
1852 if (skb == NULL) {
1853
1854
1855
1856
1857 net_dev->stats.rx_dropped++;
1858 break;
1859 }
1860 sis_priv->rx_skbuff[entry] = skb;
1861 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1862 sis_priv->rx_ring[entry].bufptr =
1863 pci_map_single(sis_priv->pci_dev, skb->data,
1864 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1865 if (unlikely(pci_dma_mapping_error(sis_priv->pci_dev,
1866 sis_priv->rx_ring[entry].bufptr))) {
1867 dev_kfree_skb_irq(skb);
1868 sis_priv->rx_skbuff[entry] = NULL;
1869 break;
1870 }
1871 }
1872 }
1873
1874 sw32(cr , RxENA | sr32(cr));
1875
1876 return 0;
1877 }
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889 static void sis900_finish_xmit (struct net_device *net_dev)
1890 {
1891 struct sis900_private *sis_priv = netdev_priv(net_dev);
1892
1893 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1894 struct sk_buff *skb;
1895 unsigned int entry;
1896 u32 tx_status;
1897
1898 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1899 tx_status = sis_priv->tx_ring[entry].cmdsts;
1900
1901 if (tx_status & OWN) {
1902
1903
1904
1905 break;
1906 }
1907
1908 if (tx_status & (ABORT | UNDERRUN | OWCOLL)) {
1909
1910 if (netif_msg_tx_err(sis_priv))
1911 printk(KERN_DEBUG "%s: Transmit "
1912 "error, Tx status %8.8x.\n",
1913 net_dev->name, tx_status);
1914 net_dev->stats.tx_errors++;
1915 if (tx_status & UNDERRUN)
1916 net_dev->stats.tx_fifo_errors++;
1917 if (tx_status & ABORT)
1918 net_dev->stats.tx_aborted_errors++;
1919 if (tx_status & NOCARRIER)
1920 net_dev->stats.tx_carrier_errors++;
1921 if (tx_status & OWCOLL)
1922 net_dev->stats.tx_window_errors++;
1923 } else {
1924
1925 net_dev->stats.collisions += (tx_status & COLCNT) >> 16;
1926 net_dev->stats.tx_bytes += tx_status & DSIZE;
1927 net_dev->stats.tx_packets++;
1928 }
1929
1930 skb = sis_priv->tx_skbuff[entry];
1931 pci_unmap_single(sis_priv->pci_dev,
1932 sis_priv->tx_ring[entry].bufptr, skb->len,
1933 PCI_DMA_TODEVICE);
1934 dev_consume_skb_irq(skb);
1935 sis_priv->tx_skbuff[entry] = NULL;
1936 sis_priv->tx_ring[entry].bufptr = 0;
1937 sis_priv->tx_ring[entry].cmdsts = 0;
1938 }
1939
1940 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1941 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1942
1943
1944 sis_priv->tx_full = 0;
1945 netif_wake_queue (net_dev);
1946 }
1947 }
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957 static int sis900_close(struct net_device *net_dev)
1958 {
1959 struct sis900_private *sis_priv = netdev_priv(net_dev);
1960 struct pci_dev *pdev = sis_priv->pci_dev;
1961 void __iomem *ioaddr = sis_priv->ioaddr;
1962 struct sk_buff *skb;
1963 int i;
1964
1965 netif_stop_queue(net_dev);
1966
1967
1968 sw32(imr, 0x0000);
1969 sw32(ier, 0x0000);
1970
1971
1972 sw32(cr, RxDIS | TxDIS | sr32(cr));
1973
1974 del_timer(&sis_priv->timer);
1975
1976 free_irq(pdev->irq, net_dev);
1977
1978
1979 for (i = 0; i < NUM_RX_DESC; i++) {
1980 skb = sis_priv->rx_skbuff[i];
1981 if (skb) {
1982 pci_unmap_single(pdev, sis_priv->rx_ring[i].bufptr,
1983 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1984 dev_kfree_skb(skb);
1985 sis_priv->rx_skbuff[i] = NULL;
1986 }
1987 }
1988 for (i = 0; i < NUM_TX_DESC; i++) {
1989 skb = sis_priv->tx_skbuff[i];
1990 if (skb) {
1991 pci_unmap_single(pdev, sis_priv->tx_ring[i].bufptr,
1992 skb->len, PCI_DMA_TODEVICE);
1993 dev_kfree_skb(skb);
1994 sis_priv->tx_skbuff[i] = NULL;
1995 }
1996 }
1997
1998
1999
2000 return 0;
2001 }
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011 static void sis900_get_drvinfo(struct net_device *net_dev,
2012 struct ethtool_drvinfo *info)
2013 {
2014 struct sis900_private *sis_priv = netdev_priv(net_dev);
2015
2016 strlcpy(info->driver, SIS900_MODULE_NAME, sizeof(info->driver));
2017 strlcpy(info->version, SIS900_DRV_VERSION, sizeof(info->version));
2018 strlcpy(info->bus_info, pci_name(sis_priv->pci_dev),
2019 sizeof(info->bus_info));
2020 }
2021
2022 static u32 sis900_get_msglevel(struct net_device *net_dev)
2023 {
2024 struct sis900_private *sis_priv = netdev_priv(net_dev);
2025 return sis_priv->msg_enable;
2026 }
2027
2028 static void sis900_set_msglevel(struct net_device *net_dev, u32 value)
2029 {
2030 struct sis900_private *sis_priv = netdev_priv(net_dev);
2031 sis_priv->msg_enable = value;
2032 }
2033
2034 static u32 sis900_get_link(struct net_device *net_dev)
2035 {
2036 struct sis900_private *sis_priv = netdev_priv(net_dev);
2037 return mii_link_ok(&sis_priv->mii_info);
2038 }
2039
2040 static int sis900_get_link_ksettings(struct net_device *net_dev,
2041 struct ethtool_link_ksettings *cmd)
2042 {
2043 struct sis900_private *sis_priv = netdev_priv(net_dev);
2044 spin_lock_irq(&sis_priv->lock);
2045 mii_ethtool_get_link_ksettings(&sis_priv->mii_info, cmd);
2046 spin_unlock_irq(&sis_priv->lock);
2047 return 0;
2048 }
2049
2050 static int sis900_set_link_ksettings(struct net_device *net_dev,
2051 const struct ethtool_link_ksettings *cmd)
2052 {
2053 struct sis900_private *sis_priv = netdev_priv(net_dev);
2054 int rt;
2055 spin_lock_irq(&sis_priv->lock);
2056 rt = mii_ethtool_set_link_ksettings(&sis_priv->mii_info, cmd);
2057 spin_unlock_irq(&sis_priv->lock);
2058 return rt;
2059 }
2060
2061 static int sis900_nway_reset(struct net_device *net_dev)
2062 {
2063 struct sis900_private *sis_priv = netdev_priv(net_dev);
2064 return mii_nway_restart(&sis_priv->mii_info);
2065 }
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078 static int sis900_set_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2079 {
2080 struct sis900_private *sis_priv = netdev_priv(net_dev);
2081 void __iomem *ioaddr = sis_priv->ioaddr;
2082 u32 cfgpmcsr = 0, pmctrl_bits = 0;
2083
2084 if (wol->wolopts == 0) {
2085 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2086 cfgpmcsr &= ~PME_EN;
2087 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2088 sw32(pmctrl, pmctrl_bits);
2089 if (netif_msg_wol(sis_priv))
2090 printk(KERN_DEBUG "%s: Wake on LAN disabled\n", net_dev->name);
2091 return 0;
2092 }
2093
2094 if (wol->wolopts & (WAKE_MAGICSECURE | WAKE_UCAST | WAKE_MCAST
2095 | WAKE_BCAST | WAKE_ARP))
2096 return -EINVAL;
2097
2098 if (wol->wolopts & WAKE_MAGIC)
2099 pmctrl_bits |= MAGICPKT;
2100 if (wol->wolopts & WAKE_PHY)
2101 pmctrl_bits |= LINKON;
2102
2103 sw32(pmctrl, pmctrl_bits);
2104
2105 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2106 cfgpmcsr |= PME_EN;
2107 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2108 if (netif_msg_wol(sis_priv))
2109 printk(KERN_DEBUG "%s: Wake on LAN enabled\n", net_dev->name);
2110
2111 return 0;
2112 }
2113
2114 static void sis900_get_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2115 {
2116 struct sis900_private *sp = netdev_priv(net_dev);
2117 void __iomem *ioaddr = sp->ioaddr;
2118 u32 pmctrl_bits;
2119
2120 pmctrl_bits = sr32(pmctrl);
2121 if (pmctrl_bits & MAGICPKT)
2122 wol->wolopts |= WAKE_MAGIC;
2123 if (pmctrl_bits & LINKON)
2124 wol->wolopts |= WAKE_PHY;
2125
2126 wol->supported = (WAKE_PHY | WAKE_MAGIC);
2127 }
2128
2129 static int sis900_get_eeprom_len(struct net_device *dev)
2130 {
2131 struct sis900_private *sis_priv = netdev_priv(dev);
2132
2133 return sis_priv->eeprom_size;
2134 }
2135
2136 static int sis900_read_eeprom(struct net_device *net_dev, u8 *buf)
2137 {
2138 struct sis900_private *sis_priv = netdev_priv(net_dev);
2139 void __iomem *ioaddr = sis_priv->ioaddr;
2140 int wait, ret = -EAGAIN;
2141 u16 signature;
2142 u16 *ebuf = (u16 *)buf;
2143 int i;
2144
2145 if (sis_priv->chipset_rev == SIS96x_900_REV) {
2146 sw32(mear, EEREQ);
2147 for (wait = 0; wait < 2000; wait++) {
2148 if (sr32(mear) & EEGNT) {
2149
2150 for (i = 0; i < sis_priv->eeprom_size / 2; i++)
2151 ebuf[i] = (u16)read_eeprom(ioaddr, i);
2152 ret = 0;
2153 break;
2154 }
2155 udelay(1);
2156 }
2157 sw32(mear, EEDONE);
2158 } else {
2159 signature = (u16)read_eeprom(ioaddr, EEPROMSignature);
2160 if (signature != 0xffff && signature != 0x0000) {
2161
2162 for (i = 0; i < sis_priv->eeprom_size / 2; i++)
2163 ebuf[i] = (u16)read_eeprom(ioaddr, i);
2164 ret = 0;
2165 }
2166 }
2167 return ret;
2168 }
2169
2170 #define SIS900_EEPROM_MAGIC 0xBABE
2171 static int sis900_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
2172 {
2173 struct sis900_private *sis_priv = netdev_priv(dev);
2174 u8 *eebuf;
2175 int res;
2176
2177 eebuf = kmalloc(sis_priv->eeprom_size, GFP_KERNEL);
2178 if (!eebuf)
2179 return -ENOMEM;
2180
2181 eeprom->magic = SIS900_EEPROM_MAGIC;
2182 spin_lock_irq(&sis_priv->lock);
2183 res = sis900_read_eeprom(dev, eebuf);
2184 spin_unlock_irq(&sis_priv->lock);
2185 if (!res)
2186 memcpy(data, eebuf + eeprom->offset, eeprom->len);
2187 kfree(eebuf);
2188 return res;
2189 }
2190
2191 static const struct ethtool_ops sis900_ethtool_ops = {
2192 .get_drvinfo = sis900_get_drvinfo,
2193 .get_msglevel = sis900_get_msglevel,
2194 .set_msglevel = sis900_set_msglevel,
2195 .get_link = sis900_get_link,
2196 .nway_reset = sis900_nway_reset,
2197 .get_wol = sis900_get_wol,
2198 .set_wol = sis900_set_wol,
2199 .get_link_ksettings = sis900_get_link_ksettings,
2200 .set_link_ksettings = sis900_set_link_ksettings,
2201 .get_eeprom_len = sis900_get_eeprom_len,
2202 .get_eeprom = sis900_get_eeprom,
2203 };
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214 static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2215 {
2216 struct sis900_private *sis_priv = netdev_priv(net_dev);
2217 struct mii_ioctl_data *data = if_mii(rq);
2218
2219 switch(cmd) {
2220 case SIOCGMIIPHY:
2221 data->phy_id = sis_priv->mii->phy_addr;
2222
2223
2224 case SIOCGMIIREG:
2225 data->val_out = mdio_read(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
2226 return 0;
2227
2228 case SIOCSMIIREG:
2229 mdio_write(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2230 return 0;
2231 default:
2232 return -EOPNOTSUPP;
2233 }
2234 }
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246 static int sis900_set_config(struct net_device *dev, struct ifmap *map)
2247 {
2248 struct sis900_private *sis_priv = netdev_priv(dev);
2249 struct mii_phy *mii_phy = sis_priv->mii;
2250
2251 u16 status;
2252
2253 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
2254
2255
2256
2257
2258
2259
2260 switch(map->port){
2261 case IF_PORT_UNKNOWN:
2262 dev->if_port = map->port;
2263
2264
2265
2266
2267
2268 netif_carrier_off(dev);
2269
2270
2271 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2272
2273
2274
2275
2276
2277 mdio_write(dev, mii_phy->phy_addr,
2278 MII_CONTROL, status | MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
2279
2280 break;
2281
2282 case IF_PORT_10BASET:
2283 dev->if_port = map->port;
2284
2285
2286
2287
2288
2289
2290 netif_carrier_off(dev);
2291
2292
2293
2294 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2295
2296
2297 mdio_write(dev, mii_phy->phy_addr,
2298 MII_CONTROL, status & ~(MII_CNTL_SPEED |
2299 MII_CNTL_AUTO));
2300 break;
2301
2302 case IF_PORT_100BASET:
2303 case IF_PORT_100BASETX:
2304 dev->if_port = map->port;
2305
2306
2307
2308
2309
2310
2311 netif_carrier_off(dev);
2312
2313
2314
2315 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2316 mdio_write(dev, mii_phy->phy_addr,
2317 MII_CONTROL, (status & ~MII_CNTL_SPEED) |
2318 MII_CNTL_SPEED);
2319
2320 break;
2321
2322 case IF_PORT_10BASE2:
2323 case IF_PORT_AUI:
2324 case IF_PORT_100BASEFX:
2325
2326 return -EOPNOTSUPP;
2327
2328 default:
2329 return -EINVAL;
2330 }
2331 }
2332 return 0;
2333 }
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346 static inline u16 sis900_mcast_bitnr(u8 *addr, u8 revision)
2347 {
2348
2349 u32 crc = ether_crc(6, addr);
2350
2351
2352 if ((revision >= SIS635A_900_REV) || (revision == SIS900B_900_REV))
2353 return (int)(crc >> 24);
2354 else
2355 return (int)(crc >> 25);
2356 }
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367 static void set_rx_mode(struct net_device *net_dev)
2368 {
2369 struct sis900_private *sis_priv = netdev_priv(net_dev);
2370 void __iomem *ioaddr = sis_priv->ioaddr;
2371 u16 mc_filter[16] = {0};
2372 int i, table_entries;
2373 u32 rx_mode;
2374
2375
2376 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2377 (sis_priv->chipset_rev == SIS900B_900_REV))
2378 table_entries = 16;
2379 else
2380 table_entries = 8;
2381
2382 if (net_dev->flags & IFF_PROMISC) {
2383
2384 rx_mode = RFPromiscuous;
2385 for (i = 0; i < table_entries; i++)
2386 mc_filter[i] = 0xffff;
2387 } else if ((netdev_mc_count(net_dev) > multicast_filter_limit) ||
2388 (net_dev->flags & IFF_ALLMULTI)) {
2389
2390 rx_mode = RFAAB | RFAAM;
2391 for (i = 0; i < table_entries; i++)
2392 mc_filter[i] = 0xffff;
2393 } else {
2394
2395
2396
2397 struct netdev_hw_addr *ha;
2398 rx_mode = RFAAB;
2399
2400 netdev_for_each_mc_addr(ha, net_dev) {
2401 unsigned int bit_nr;
2402
2403 bit_nr = sis900_mcast_bitnr(ha->addr,
2404 sis_priv->chipset_rev);
2405 mc_filter[bit_nr >> 4] |= (1 << (bit_nr & 0xf));
2406 }
2407 }
2408
2409
2410 for (i = 0; i < table_entries; i++) {
2411
2412 sw32(rfcr, (u32)(0x00000004 + i) << RFADDR_shift);
2413 sw32(rfdr, mc_filter[i]);
2414 }
2415
2416 sw32(rfcr, RFEN | rx_mode);
2417
2418
2419
2420 if (net_dev->flags & IFF_LOOPBACK) {
2421 u32 cr_saved;
2422
2423 cr_saved = sr32(cr);
2424 sw32(cr, cr_saved | TxDIS | RxDIS);
2425
2426 sw32(txcfg, sr32(txcfg) | TxMLB);
2427 sw32(rxcfg, sr32(rxcfg) | RxATX);
2428
2429 sw32(cr, cr_saved);
2430 }
2431 }
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442 static void sis900_reset(struct net_device *net_dev)
2443 {
2444 struct sis900_private *sis_priv = netdev_priv(net_dev);
2445 void __iomem *ioaddr = sis_priv->ioaddr;
2446 u32 status = TxRCMP | RxRCMP;
2447 int i;
2448
2449 sw32(ier, 0);
2450 sw32(imr, 0);
2451 sw32(rfcr, 0);
2452
2453 sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));
2454
2455
2456 for (i = 0; status && (i < 1000); i++)
2457 status ^= sr32(isr) & status;
2458
2459 if (sis_priv->chipset_rev >= SIS635A_900_REV ||
2460 sis_priv->chipset_rev == SIS900B_900_REV)
2461 sw32(cfg, PESEL | RND_CNT);
2462 else
2463 sw32(cfg, PESEL);
2464 }
2465
2466
2467
2468
2469
2470
2471
2472
2473 static void sis900_remove(struct pci_dev *pci_dev)
2474 {
2475 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2476 struct sis900_private *sis_priv = netdev_priv(net_dev);
2477
2478 unregister_netdev(net_dev);
2479
2480 while (sis_priv->first_mii) {
2481 struct mii_phy *phy = sis_priv->first_mii;
2482
2483 sis_priv->first_mii = phy->next;
2484 kfree(phy);
2485 }
2486
2487 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2488 sis_priv->rx_ring_dma);
2489 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2490 sis_priv->tx_ring_dma);
2491 pci_iounmap(pci_dev, sis_priv->ioaddr);
2492 free_netdev(net_dev);
2493 pci_release_regions(pci_dev);
2494 }
2495
2496 #ifdef CONFIG_PM
2497
2498 static int sis900_suspend(struct pci_dev *pci_dev, pm_message_t state)
2499 {
2500 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2501 struct sis900_private *sis_priv = netdev_priv(net_dev);
2502 void __iomem *ioaddr = sis_priv->ioaddr;
2503
2504 if(!netif_running(net_dev))
2505 return 0;
2506
2507 netif_stop_queue(net_dev);
2508 netif_device_detach(net_dev);
2509
2510
2511 sw32(cr, RxDIS | TxDIS | sr32(cr));
2512
2513 pci_set_power_state(pci_dev, PCI_D3hot);
2514 pci_save_state(pci_dev);
2515
2516 return 0;
2517 }
2518
2519 static int sis900_resume(struct pci_dev *pci_dev)
2520 {
2521 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2522 struct sis900_private *sis_priv = netdev_priv(net_dev);
2523 void __iomem *ioaddr = sis_priv->ioaddr;
2524
2525 if(!netif_running(net_dev))
2526 return 0;
2527 pci_restore_state(pci_dev);
2528 pci_set_power_state(pci_dev, PCI_D0);
2529
2530 sis900_init_rxfilter(net_dev);
2531
2532 sis900_init_tx_ring(net_dev);
2533 sis900_init_rx_ring(net_dev);
2534
2535 set_rx_mode(net_dev);
2536
2537 netif_device_attach(net_dev);
2538 netif_start_queue(net_dev);
2539
2540
2541 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
2542
2543
2544 sw32(imr, RxSOVR | RxORN | RxERR | RxOK | TxURN | TxERR | TxDESC);
2545 sw32(cr, RxENA | sr32(cr));
2546 sw32(ier, IE);
2547
2548 sis900_check_mode(net_dev, sis_priv->mii);
2549
2550 return 0;
2551 }
2552 #endif
2553
2554 static struct pci_driver sis900_pci_driver = {
2555 .name = SIS900_MODULE_NAME,
2556 .id_table = sis900_pci_tbl,
2557 .probe = sis900_probe,
2558 .remove = sis900_remove,
2559 #ifdef CONFIG_PM
2560 .suspend = sis900_suspend,
2561 .resume = sis900_resume,
2562 #endif
2563 };
2564
2565 static int __init sis900_init_module(void)
2566 {
2567
2568 #ifdef MODULE
2569 printk(version);
2570 #endif
2571
2572 return pci_register_driver(&sis900_pci_driver);
2573 }
2574
2575 static void __exit sis900_cleanup_module(void)
2576 {
2577 pci_unregister_driver(&sis900_pci_driver);
2578 }
2579
2580 module_init(sis900_init_module);
2581 module_exit(sis900_cleanup_module);
2582