1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell OcteonTx2 CGX driver
3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #ifndef __CGX_FW_INTF_H__
12 #define __CGX_FW_INTF_H__
13
14 #include <linux/bitops.h>
15 #include <linux/bitfield.h>
16
17 #define CGX_FIRMWARE_MAJOR_VER 1
18 #define CGX_FIRMWARE_MINOR_VER 0
19
20 #define CGX_EVENT_ACK 1UL
21
22 /* CGX error types. set for cmd response status as CGX_STAT_FAIL */
23 enum cgx_error_type {
24 CGX_ERR_NONE,
25 CGX_ERR_LMAC_NOT_ENABLED,
26 CGX_ERR_LMAC_MODE_INVALID,
27 CGX_ERR_REQUEST_ID_INVALID,
28 CGX_ERR_PREV_ACK_NOT_CLEAR,
29 CGX_ERR_PHY_LINK_DOWN,
30 CGX_ERR_PCS_RESET_FAIL,
31 CGX_ERR_AN_CPT_FAIL,
32 CGX_ERR_TX_NOT_IDLE,
33 CGX_ERR_RX_NOT_IDLE,
34 CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
35 CGX_ERR_SPUX_RX_ALIGN_FAIL,
36 CGX_ERR_SPUX_TX_FAULT,
37 CGX_ERR_SPUX_RX_FAULT,
38 CGX_ERR_SPUX_RESET_FAIL,
39 CGX_ERR_SPUX_AN_RESET_FAIL,
40 CGX_ERR_SPUX_USX_AN_RESET_FAIL,
41 CGX_ERR_SMUX_RX_LINK_NOT_OK,
42 CGX_ERR_PCS_RECV_LINK_FAIL,
43 CGX_ERR_TRAINING_FAIL,
44 CGX_ERR_RX_EQU_FAIL,
45 CGX_ERR_SPUX_BER_FAIL,
46 CGX_ERR_SPUX_RSFEC_ALGN_FAIL, /* = 22 */
47 };
48
49 /* LINK speed types */
50 enum cgx_link_speed {
51 CGX_LINK_NONE,
52 CGX_LINK_10M,
53 CGX_LINK_100M,
54 CGX_LINK_1G,
55 CGX_LINK_2HG,
56 CGX_LINK_5G,
57 CGX_LINK_10G,
58 CGX_LINK_20G,
59 CGX_LINK_25G,
60 CGX_LINK_40G,
61 CGX_LINK_50G,
62 CGX_LINK_100G,
63 CGX_LINK_SPEED_MAX,
64 };
65
66 /* REQUEST ID types. Input to firmware */
67 enum cgx_cmd_id {
68 CGX_CMD_NONE,
69 CGX_CMD_GET_FW_VER,
70 CGX_CMD_GET_MAC_ADDR,
71 CGX_CMD_SET_MTU,
72 CGX_CMD_GET_LINK_STS, /* optional to user */
73 CGX_CMD_LINK_BRING_UP,
74 CGX_CMD_LINK_BRING_DOWN,
75 CGX_CMD_INTERNAL_LBK,
76 CGX_CMD_EXTERNAL_LBK,
77 CGX_CMD_HIGIG,
78 CGX_CMD_LINK_STATE_CHANGE,
79 CGX_CMD_MODE_CHANGE, /* hot plug support */
80 CGX_CMD_INTF_SHUTDOWN,
81 CGX_CMD_GET_MKEX_PRFL_SIZE,
82 CGX_CMD_GET_MKEX_PRFL_ADDR
83 };
84
85 /* async event ids */
86 enum cgx_evt_id {
87 CGX_EVT_NONE,
88 CGX_EVT_LINK_CHANGE,
89 };
90
91 /* event types - cause of interrupt */
92 enum cgx_evt_type {
93 CGX_EVT_ASYNC,
94 CGX_EVT_CMD_RESP
95 };
96
97 enum cgx_stat {
98 CGX_STAT_SUCCESS,
99 CGX_STAT_FAIL
100 };
101
102 enum cgx_cmd_own {
103 CGX_CMD_OWN_NS,
104 CGX_CMD_OWN_FIRMWARE,
105 };
106
107 /* m - bit mask
108 * y - value to be written in the bitrange
109 * x - input value whose bitrange to be modified
110 */
111 #define FIELD_SET(m, y, x) \
112 (((x) & ~(m)) | \
113 FIELD_PREP((m), (y)))
114
115 /* scratchx(0) CSR used for ATF->non-secure SW communication.
116 * This acts as the status register
117 * Provides details on command ack/status, command response, error details
118 */
119 #define EVTREG_ACK BIT_ULL(0)
120 #define EVTREG_EVT_TYPE BIT_ULL(1)
121 #define EVTREG_STAT BIT_ULL(2)
122 #define EVTREG_ID GENMASK_ULL(8, 3)
123
124 /* Response to command IDs with command status as CGX_STAT_FAIL
125 *
126 * Not applicable for commands :
127 * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
128 */
129 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
130
131 /* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
132 * CGX_STAT_SUCCESS
133 */
134 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
135 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
136
137 /* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
138 * CGX_STAT_SUCCESS
139 */
140 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
141
142 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as
143 * CGX_STAT_SUCCESS
144 */
145 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9)
146
147 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as
148 * CGX_STAT_SUCCESS
149 */
150 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9)
151
152 /* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
153 * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
154 *
155 * In case of CGX_STAT_FAIL, it indicates CGX configuration failed
156 * when processing link up/down/change command.
157 * Both err_type and current link status will be updated
158 *
159 * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
160 * link status will be updated
161 */
162 struct cgx_lnk_sts {
163 uint64_t reserved1:9;
164 uint64_t link_up:1;
165 uint64_t full_duplex:1;
166 uint64_t speed:4; /* cgx_link_speed */
167 uint64_t err_type:10;
168 uint64_t reserved2:39;
169 };
170
171 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
172 #define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10)
173 #define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11)
174 #define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15)
175
176 /* scratchx(1) CSR used for non-secure SW->ATF communication
177 * This CSR acts as a command register
178 */
179 #define CMDREG_OWN BIT_ULL(0)
180 #define CMDREG_ID GENMASK_ULL(7, 2)
181
182 /* Any command using enable/disable as an argument need
183 * to set this bitfield.
184 * Ex: Loopback, HiGig...
185 */
186 #define CMDREG_ENABLE BIT_ULL(8)
187
188 /* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
189 #define CMDMTU_SIZE GENMASK_ULL(23, 8)
190
191 /* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
192 #define CMDLINKCHANGE_LINKUP BIT_ULL(8)
193 #define CMDLINKCHANGE_FULLDPLX BIT_ULL(9)
194 #define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10)
195
196 #endif /* __CGX_FW_INTF_H__ */