This source file includes following definitions.
- hns_dsaf_dev_priv
- hns_dsaf_tbl_tcam_addr_cfg
- hns_dsaf_tbl_tcam_load_pul
- hns_dsaf_tbl_line_addr_cfg
- hns_ae_get_vf_cb
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6 #ifndef __HNS_DSAF_MAIN_H
7 #define __HNS_DSAF_MAIN_H
8 #include "hnae.h"
9
10 #include "hns_dsaf_reg.h"
11 #include "hns_dsaf_mac.h"
12
13 struct hns_mac_cb;
14
15 #define DSAF_DRV_NAME "hns_dsaf"
16 #define DSAF_MOD_VERSION "v1.0"
17 #define DSAF_DEVICE_NAME "dsaf"
18
19 #define HNS_DSAF_DEBUG_NW_REG_OFFSET 0x100000
20
21 #define DSAF_BASE_INNER_PORT_NUM 127
22
23 #define DSAF_MAX_CHIP_NUM 2
24
25 #define DSAF_DEFAUTL_QUEUE_NUM_PER_PPE 22
26
27 #define HNS_DSAF_MAX_DESC_CNT 1024
28 #define HNS_DSAF_MIN_DESC_CNT 16
29
30 #define DSAF_INVALID_ENTRY_IDX 0xffff
31
32 #define DSAF_CFG_READ_CNT 30
33
34 #define DSAF_DUMP_REGS_NUM 504
35 #define DSAF_STATIC_NUM 28
36 #define DSAF_V2_STATIC_NUM 44
37 #define DSAF_PRIO_NR 8
38 #define DSAF_REG_PER_ZONE 3
39
40 #define DSAF_ROCE_CREDIT_CHN 8
41 #define DSAF_ROCE_CHAN_MODE 3
42
43 #define HNS_MAX_WAIT_CNT 10000
44
45 enum dsaf_roce_port_mode {
46 DSAF_ROCE_6PORT_MODE,
47 DSAF_ROCE_4PORT_MODE,
48 DSAF_ROCE_2PORT_MODE,
49 DSAF_ROCE_CHAN_MODE_NUM,
50 };
51
52 enum dsaf_roce_port_num {
53 DSAF_ROCE_PORT_0,
54 DSAF_ROCE_PORT_1,
55 DSAF_ROCE_PORT_2,
56 DSAF_ROCE_PORT_3,
57 DSAF_ROCE_PORT_4,
58 DSAF_ROCE_PORT_5,
59 };
60
61 enum dsaf_roce_qos_sl {
62 DSAF_ROCE_SL_0,
63 DSAF_ROCE_SL_1,
64 DSAF_ROCE_SL_2,
65 DSAF_ROCE_SL_3,
66 };
67
68 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
69 #define HNS_DSAF_IS_DEBUG(dev) ((dev)->dsaf_mode == DSAF_MODE_DISABLE_SP)
70
71 enum hal_dsaf_mode {
72 HRD_DSAF_NO_DSAF_MODE = 0x0,
73 HRD_DSAF_MODE = 0x1,
74 };
75
76 enum hal_dsaf_tc_mode {
77 HRD_DSAF_4TC_MODE = 0X0,
78 HRD_DSAF_8TC_MODE = 0X1,
79 };
80
81 struct dsaf_vm_def_vlan {
82 u32 vm_def_vlan_id;
83 u32 vm_def_vlan_cfi;
84 u32 vm_def_vlan_pri;
85 };
86
87 struct dsaf_tbl_tcam_data {
88 u32 tbl_tcam_data_high;
89 u32 tbl_tcam_data_low;
90 };
91
92 #define DSAF_PORT_MSK_NUM \
93 ((DSAF_TOTAL_QUEUE_NUM + DSAF_SERVICE_NW_NUM - 1) / 32 + 1)
94 struct dsaf_tbl_tcam_mcast_cfg {
95 u8 tbl_mcast_old_en;
96 u8 tbl_mcast_item_vld;
97 u32 tbl_mcast_port_msk[DSAF_PORT_MSK_NUM];
98 };
99
100 struct dsaf_tbl_tcam_ucast_cfg {
101 u32 tbl_ucast_old_en;
102 u32 tbl_ucast_item_vld;
103 u32 tbl_ucast_mac_discard;
104 u32 tbl_ucast_dvc;
105 u32 tbl_ucast_out_port;
106 };
107
108 struct dsaf_tbl_line_cfg {
109 u32 tbl_line_mac_discard;
110 u32 tbl_line_dvc;
111 u32 tbl_line_out_port;
112 };
113
114 enum dsaf_port_rate_mode {
115 DSAF_PORT_RATE_1000 = 0,
116 DSAF_PORT_RATE_2500,
117 DSAF_PORT_RATE_10000
118 };
119
120 enum dsaf_stp_port_type {
121 DSAF_STP_PORT_TYPE_DISCARD = 0,
122 DSAF_STP_PORT_TYPE_BLOCK = 1,
123 DSAF_STP_PORT_TYPE_LISTEN = 2,
124 DSAF_STP_PORT_TYPE_LEARN = 3,
125 DSAF_STP_PORT_TYPE_FORWARD = 4
126 };
127
128 enum dsaf_sw_port_type {
129 DSAF_SW_PORT_TYPE_NON_VLAN = 0,
130 DSAF_SW_PORT_TYPE_ACCESS = 1,
131 DSAF_SW_PORT_TYPE_TRUNK = 2,
132 };
133
134 #define DSAF_SUB_BASE_SIZE (0x10000)
135
136
137 enum dsaf_mode {
138 DSAF_MODE_INVALID = 0,
139 DSAF_MODE_ENABLE_FIX,
140 DSAF_MODE_ENABLE_0VM,
141 DSAF_MODE_ENABLE_8VM,
142 DSAF_MODE_ENABLE_16VM,
143 DSAF_MODE_ENABLE_32VM,
144 DSAF_MODE_ENABLE_128VM,
145 DSAF_MODE_ENABLE,
146 DSAF_MODE_DISABLE_SP,
147 DSAF_MODE_DISABLE_FIX,
148 DSAF_MODE_DISABLE_2PORT_8VM,
149 DSAF_MODE_DISABLE_2PORT_16VM,
150 DSAF_MODE_DISABLE_2PORT_64VM,
151 DSAF_MODE_DISABLE_6PORT_0VM,
152 DSAF_MODE_DISABLE_6PORT_2VM,
153 DSAF_MODE_DISABLE_6PORT_4VM,
154 DSAF_MODE_DISABLE_6PORT_16VM,
155 DSAF_MODE_MAX
156 };
157
158 #define DSAF_DEST_PORT_NUM 256
159 #define DSAF_WORD_BIT_CNT 32
160
161
162 struct dsaf_drv_mac_single_dest_entry {
163
164 u8 addr[ETH_ALEN];
165 u16 in_vlan_id;
166
167
168
169 u8 in_port_num;
170
171 u8 port_num;
172 u8 rsv[6];
173 };
174
175
176 struct dsaf_drv_mac_multi_dest_entry {
177
178 u8 addr[ETH_ALEN];
179 u16 in_vlan_id;
180
181
182 u32 port_mask[DSAF_DEST_PORT_NUM / DSAF_WORD_BIT_CNT];
183
184
185
186 u8 in_port_num;
187 u8 rsv[7];
188 };
189
190 struct dsaf_hw_stats {
191 u64 pad_drop;
192 u64 man_pkts;
193 u64 rx_pkts;
194 u64 rx_pkt_id;
195 u64 rx_pause_frame;
196 u64 release_buf_num;
197 u64 sbm_drop;
198 u64 crc_false;
199 u64 bp_drop;
200 u64 rslt_drop;
201 u64 local_addr_false;
202 u64 vlan_drop;
203 u64 stp_drop;
204 u64 rx_pfc[DSAF_PRIO_NR];
205 u64 tx_pfc[DSAF_PRIO_NR];
206 u64 tx_pkts;
207 };
208
209 struct hnae_vf_cb {
210 u8 port_index;
211 struct hns_mac_cb *mac_cb;
212 struct dsaf_device *dsaf_dev;
213 struct hnae_handle ae_handle;
214 };
215
216 struct dsaf_int_xge_src {
217 u32 xid_xge_ecc_err_int_src;
218 u32 xid_xge_fsm_timout_int_src;
219 u32 sbm_xge_lnk_fsm_timout_int_src;
220 u32 sbm_xge_lnk_ecc_2bit_int_src;
221 u32 sbm_xge_mib_req_failed_int_src;
222 u32 sbm_xge_mib_req_fsm_timout_int_src;
223 u32 sbm_xge_mib_rels_fsm_timout_int_src;
224 u32 sbm_xge_sram_ecc_2bit_int_src;
225 u32 sbm_xge_mib_buf_sum_err_int_src;
226 u32 sbm_xge_mib_req_extra_int_src;
227 u32 sbm_xge_mib_rels_extra_int_src;
228 u32 voq_xge_start_to_over_0_int_src;
229 u32 voq_xge_start_to_over_1_int_src;
230 u32 voq_xge_ecc_err_int_src;
231 };
232
233 struct dsaf_int_ppe_src {
234 u32 xid_ppe_fsm_timout_int_src;
235 u32 sbm_ppe_lnk_fsm_timout_int_src;
236 u32 sbm_ppe_lnk_ecc_2bit_int_src;
237 u32 sbm_ppe_mib_req_failed_int_src;
238 u32 sbm_ppe_mib_req_fsm_timout_int_src;
239 u32 sbm_ppe_mib_rels_fsm_timout_int_src;
240 u32 sbm_ppe_sram_ecc_2bit_int_src;
241 u32 sbm_ppe_mib_buf_sum_err_int_src;
242 u32 sbm_ppe_mib_req_extra_int_src;
243 u32 sbm_ppe_mib_rels_extra_int_src;
244 u32 voq_ppe_start_to_over_0_int_src;
245 u32 voq_ppe_ecc_err_int_src;
246 u32 xod_ppe_fifo_rd_empty_int_src;
247 u32 xod_ppe_fifo_wr_full_int_src;
248 };
249
250 struct dsaf_int_rocee_src {
251 u32 xid_rocee_fsm_timout_int_src;
252 u32 sbm_rocee_lnk_fsm_timout_int_src;
253 u32 sbm_rocee_lnk_ecc_2bit_int_src;
254 u32 sbm_rocee_mib_req_failed_int_src;
255 u32 sbm_rocee_mib_req_fsm_timout_int_src;
256 u32 sbm_rocee_mib_rels_fsm_timout_int_src;
257 u32 sbm_rocee_sram_ecc_2bit_int_src;
258 u32 sbm_rocee_mib_buf_sum_err_int_src;
259 u32 sbm_rocee_mib_req_extra_int_src;
260 u32 sbm_rocee_mib_rels_extra_int_src;
261 u32 voq_rocee_start_to_over_0_int_src;
262 u32 voq_rocee_ecc_err_int_src;
263 };
264
265 struct dsaf_int_tbl_src {
266 u32 tbl_da0_mis_src;
267 u32 tbl_da1_mis_src;
268 u32 tbl_da2_mis_src;
269 u32 tbl_da3_mis_src;
270 u32 tbl_da4_mis_src;
271 u32 tbl_da5_mis_src;
272 u32 tbl_da6_mis_src;
273 u32 tbl_da7_mis_src;
274 u32 tbl_sa_mis_src;
275 u32 tbl_old_sech_end_src;
276 u32 lram_ecc_err1_src;
277 u32 lram_ecc_err2_src;
278 u32 tram_ecc_err1_src;
279 u32 tram_ecc_err2_src;
280 u32 tbl_ucast_bcast_xge0_src;
281 u32 tbl_ucast_bcast_xge1_src;
282 u32 tbl_ucast_bcast_xge2_src;
283 u32 tbl_ucast_bcast_xge3_src;
284 u32 tbl_ucast_bcast_xge4_src;
285 u32 tbl_ucast_bcast_xge5_src;
286 u32 tbl_ucast_bcast_ppe_src;
287 u32 tbl_ucast_bcast_rocee_src;
288 };
289
290 struct dsaf_int_stat {
291 struct dsaf_int_xge_src dsaf_int_xge_stat[DSAF_COMM_CHN];
292 struct dsaf_int_ppe_src dsaf_int_ppe_stat[DSAF_COMM_CHN];
293 struct dsaf_int_rocee_src dsaf_int_rocee_stat[DSAF_COMM_CHN];
294 struct dsaf_int_tbl_src dsaf_int_tbl_stat[1];
295
296 };
297
298 struct dsaf_misc_op {
299 void (*cpld_set_led)(struct hns_mac_cb *mac_cb, int link_status,
300 u16 speed, int data);
301 void (*cpld_reset_led)(struct hns_mac_cb *mac_cb);
302 int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb,
303 enum hnae_led_state status);
304
305 void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset);
306 void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
307 void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
308 void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
309 void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset);
310 void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk,
311 bool dereset);
312 void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset);
313
314 phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb);
315 int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt);
316
317 int (*cfg_serdes_loopback)(struct hns_mac_cb *mac_cb, bool en);
318 };
319
320
321 struct dsaf_device {
322 struct device *dev;
323 struct hnae_ae_dev ae_dev;
324
325 u8 __iomem *sc_base;
326 u8 __iomem *sds_base;
327 u8 __iomem *ppe_base;
328 u8 __iomem *io_base;
329 struct regmap *sub_ctrl;
330 phys_addr_t ppe_paddr;
331
332 u32 desc_num;
333 u32 buf_size;
334 u32 reset_offset;
335 int buf_size_type;
336 enum dsaf_mode dsaf_mode;
337 enum hal_dsaf_mode dsaf_en;
338 enum hal_dsaf_tc_mode dsaf_tc_mode;
339 u32 dsaf_ver;
340 u16 tcam_max_num;
341
342 struct ppe_common_cb *ppe_common[DSAF_COMM_DEV_NUM];
343 struct rcb_common_cb *rcb_common[DSAF_COMM_DEV_NUM];
344 struct hns_mac_cb *mac_cb[DSAF_MAX_PORT_NUM];
345 struct dsaf_misc_op *misc_op;
346
347 struct dsaf_hw_stats hw_stats[DSAF_NODE_NUM];
348 struct dsaf_int_stat int_stat;
349
350 spinlock_t tcam_lock;
351 };
352
353 static inline void *hns_dsaf_dev_priv(const struct dsaf_device *dsaf_dev)
354 {
355 return (void *)((u8 *)dsaf_dev + sizeof(*dsaf_dev));
356 }
357
358 #define DSAF_TBL_TCAM_KEY_PORT_S 0
359 #define DSAF_TBL_TCAM_KEY_PORT_M (((1ULL << 4) - 1) << 0)
360 #define DSAF_TBL_TCAM_KEY_VLAN_S 4
361 #define DSAF_TBL_TCAM_KEY_VLAN_M (((1ULL << 12) - 1) << 4)
362
363 struct dsaf_drv_tbl_tcam_key {
364 union {
365 struct {
366 u8 mac_3;
367 u8 mac_2;
368 u8 mac_1;
369 u8 mac_0;
370 } bits;
371
372 u32 val;
373 } high;
374 union {
375 struct {
376 u16 port_vlan;
377 u8 mac_5;
378 u8 mac_4;
379 } bits;
380
381 u32 val;
382 } low;
383 };
384
385 struct dsaf_drv_soft_mac_tbl {
386 struct dsaf_drv_tbl_tcam_key tcam_key;
387 u16 index;
388 };
389
390 struct dsaf_drv_priv {
391
392 struct dsaf_drv_soft_mac_tbl *soft_mac_tbl;
393 };
394
395 static inline void hns_dsaf_tbl_tcam_addr_cfg(struct dsaf_device *dsaf_dev,
396 u32 tab_tcam_addr)
397 {
398 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
399 DSAF_TBL_TCAM_ADDR_M, DSAF_TBL_TCAM_ADDR_S,
400 tab_tcam_addr);
401 }
402
403 static inline void hns_dsaf_tbl_tcam_load_pul(struct dsaf_device *dsaf_dev)
404 {
405 u32 o_tbl_pul;
406
407 o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
408 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 1);
409 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
410 dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_LOAD_S, 0);
411 dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
412 }
413
414 static inline void hns_dsaf_tbl_line_addr_cfg(struct dsaf_device *dsaf_dev,
415 u32 tab_line_addr)
416 {
417 dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
418 DSAF_TBL_LINE_ADDR_M, DSAF_TBL_LINE_ADDR_S,
419 tab_line_addr);
420 }
421
422 static inline struct hnae_vf_cb *hns_ae_get_vf_cb(
423 struct hnae_handle *handle)
424 {
425 return container_of(handle, struct hnae_vf_cb, ae_handle);
426 }
427
428 int hns_dsaf_set_mac_uc_entry(struct dsaf_device *dsaf_dev,
429 struct dsaf_drv_mac_single_dest_entry *mac_entry);
430 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
431 struct dsaf_drv_mac_single_dest_entry *mac_entry);
432 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
433 u8 in_port_num, u8 *addr);
434 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
435 struct dsaf_drv_mac_single_dest_entry *mac_entry);
436 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
437
438 int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
439 void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);
440
441 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 inode_num);
442
443 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset);
444 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port);
445 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
446 struct dsaf_device *dsaf_dev);
447
448 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data);
449 int hns_dsaf_get_regs_count(void);
450 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en);
451 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
452 u32 port, bool enable);
453
454 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
455 u32 *en);
456 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
457 u32 en);
458 int hns_dsaf_rm_mac_addr(
459 struct dsaf_device *dsaf_dev,
460 struct dsaf_drv_mac_single_dest_entry *mac_entry);
461
462 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev,
463 u8 mac_id, u8 port_num);
464 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port);
465
466 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
467
468 #endif