drivers/net/ethernet/stmicro/stmmac/stmmac

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This source file includes following definitions.
stmmac_pci_find_phy_addr
common_default_data
stmmac_default_data
intel_mgbe_common_data
ehl_common_data
ehl_sgmii_data
ehl_rgmii_data
tgl_common_data
tgl_sgmii_data
quark_default_data
snps_gmac5_default_data
stmmac_pci_probe
stmmac_pci_remove
stmmac_pci_suspend
stmmac_pci_resume
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This contains the functions to handle the pci driver.
   4 
   5   Copyright (C) 2011-2012  Vayavya Labs Pvt Ltd
   6 
   7 
   8   Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10 *******************************************************************************/
  11 
  12 #include <linux/clk-provider.h>
  13 #include <linux/pci.h>
  14 #include <linux/dmi.h>
  15 
  16 #include "stmmac.h"
  17 
  18 /*
  19  * This struct is used to associate PCI Function of MAC controller on a board,
  20  * discovered via DMI, with the address of PHY connected to the MAC. The
  21  * negative value of the address means that MAC controller is not connected
  22  * with PHY.
  23  */
  24 struct stmmac_pci_func_data {
  25         unsigned int func;
  26         int phy_addr;
  27 };
  28 
  29 struct stmmac_pci_dmi_data {
  30         const struct stmmac_pci_func_data *func;
  31         size_t nfuncs;
  32 };
  33 
  34 struct stmmac_pci_info {
  35         int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
  36 };
  37 
  38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
  39                                     const struct dmi_system_id *dmi_list)
  40 {
  41         const struct stmmac_pci_func_data *func_data;
  42         const struct stmmac_pci_dmi_data *dmi_data;
  43         const struct dmi_system_id *dmi_id;
  44         int func = PCI_FUNC(pdev->devfn);
  45         size_t n;
  46 
  47         dmi_id = dmi_first_match(dmi_list);
  48         if (!dmi_id)
  49                 return -ENODEV;
  50 
  51         dmi_data = dmi_id->driver_data;
  52         func_data = dmi_data->func;
  53 
  54         for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
  55                 if (func_data->func == func)
  56                         return func_data->phy_addr;
  57 
  58         return -ENODEV;
  59 }
  60 
  61 static void common_default_data(struct plat_stmmacenet_data *plat)
  62 {
  63         plat->clk_csr = 2;      /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
  64         plat->has_gmac = 1;
  65         plat->force_sf_dma_mode = 1;
  66 
  67         plat->mdio_bus_data->needs_reset = true;
  68         plat->mdio_bus_data->phy_mask = 0;
  69 
  70         /* Set default value for multicast hash bins */
  71         plat->multicast_filter_bins = HASH_TABLE_SIZE;
  72 
  73         /* Set default value for unicast filter entries */
  74         plat->unicast_filter_entries = 1;
  75 
  76         /* Set the maxmtu to a default of JUMBO_LEN */
  77         plat->maxmtu = JUMBO_LEN;
  78 
  79         /* Set default number of RX and TX queues to use */
  80         plat->tx_queues_to_use = 1;
  81         plat->rx_queues_to_use = 1;
  82 
  83         /* Disable Priority config by default */
  84         plat->tx_queues_cfg[0].use_prio = false;
  85         plat->rx_queues_cfg[0].use_prio = false;
  86 
  87         /* Disable RX queues routing by default */
  88         plat->rx_queues_cfg[0].pkt_route = 0x0;
  89 }
  90 
  91 static int stmmac_default_data(struct pci_dev *pdev,
  92                                struct plat_stmmacenet_data *plat)
  93 {
  94         /* Set common default data first */
  95         common_default_data(plat);
  96 
  97         plat->bus_id = 1;
  98         plat->phy_addr = 0;
  99         plat->interface = PHY_INTERFACE_MODE_GMII;
 100 
 101         plat->dma_cfg->pbl = 32;
 102         plat->dma_cfg->pblx8 = true;
 103         /* TODO: AXI */
 104 
 105         return 0;
 106 }
 107 
 108 static const struct stmmac_pci_info stmmac_pci_info = {
 109         .setup = stmmac_default_data,
 110 };
 111 
 112 static int intel_mgbe_common_data(struct pci_dev *pdev,
 113                                   struct plat_stmmacenet_data *plat)
 114 {
 115         int i;
 116 
 117         plat->clk_csr = 5;
 118         plat->has_gmac = 0;
 119         plat->has_gmac4 = 1;
 120         plat->force_sf_dma_mode = 0;
 121         plat->tso_en = 1;
 122 
 123         plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
 124 
 125         for (i = 0; i < plat->rx_queues_to_use; i++) {
 126                 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
 127                 plat->rx_queues_cfg[i].chan = i;
 128 
 129                 /* Disable Priority config by default */
 130                 plat->rx_queues_cfg[i].use_prio = false;
 131 
 132                 /* Disable RX queues routing by default */
 133                 plat->rx_queues_cfg[i].pkt_route = 0x0;
 134         }
 135 
 136         for (i = 0; i < plat->tx_queues_to_use; i++) {
 137                 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
 138 
 139                 /* Disable Priority config by default */
 140                 plat->tx_queues_cfg[i].use_prio = false;
 141         }
 142 
 143         /* FIFO size is 4096 bytes for 1 tx/rx queue */
 144         plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
 145         plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
 146 
 147         plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
 148         plat->tx_queues_cfg[0].weight = 0x09;
 149         plat->tx_queues_cfg[1].weight = 0x0A;
 150         plat->tx_queues_cfg[2].weight = 0x0B;
 151         plat->tx_queues_cfg[3].weight = 0x0C;
 152         plat->tx_queues_cfg[4].weight = 0x0D;
 153         plat->tx_queues_cfg[5].weight = 0x0E;
 154         plat->tx_queues_cfg[6].weight = 0x0F;
 155         plat->tx_queues_cfg[7].weight = 0x10;
 156 
 157         plat->mdio_bus_data->phy_mask = 0;
 158 
 159         plat->dma_cfg->pbl = 32;
 160         plat->dma_cfg->pblx8 = true;
 161         plat->dma_cfg->fixed_burst = 0;
 162         plat->dma_cfg->mixed_burst = 0;
 163         plat->dma_cfg->aal = 0;
 164 
 165         plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
 166                                  GFP_KERNEL);
 167         if (!plat->axi)
 168                 return -ENOMEM;
 169 
 170         plat->axi->axi_lpi_en = 0;
 171         plat->axi->axi_xit_frm = 0;
 172         plat->axi->axi_wr_osr_lmt = 1;
 173         plat->axi->axi_rd_osr_lmt = 1;
 174         plat->axi->axi_blen[0] = 4;
 175         plat->axi->axi_blen[1] = 8;
 176         plat->axi->axi_blen[2] = 16;
 177 
 178         plat->ptp_max_adj = plat->clk_ptp_rate;
 179 
 180         /* Set system clock */
 181         plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
 182                                                    "stmmac-clk", NULL, 0,
 183                                                    plat->clk_ptp_rate);
 184 
 185         if (IS_ERR(plat->stmmac_clk)) {
 186                 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
 187                 plat->stmmac_clk = NULL;
 188         }
 189         clk_prepare_enable(plat->stmmac_clk);
 190 
 191         /* Set default value for multicast hash bins */
 192         plat->multicast_filter_bins = HASH_TABLE_SIZE;
 193 
 194         /* Set default value for unicast filter entries */
 195         plat->unicast_filter_entries = 1;
 196 
 197         /* Set the maxmtu to a default of JUMBO_LEN */
 198         plat->maxmtu = JUMBO_LEN;
 199 
 200         return 0;
 201 }
 202 
 203 static int ehl_common_data(struct pci_dev *pdev,
 204                            struct plat_stmmacenet_data *plat)
 205 {
 206         int ret;
 207 
 208         plat->rx_queues_to_use = 8;
 209         plat->tx_queues_to_use = 8;
 210         plat->clk_ptp_rate = 200000000;
 211         ret = intel_mgbe_common_data(pdev, plat);
 212         if (ret)
 213                 return ret;
 214 
 215         return 0;
 216 }
 217 
 218 static int ehl_sgmii_data(struct pci_dev *pdev,
 219                           struct plat_stmmacenet_data *plat)
 220 {
 221         plat->bus_id = 1;
 222         plat->phy_addr = 0;
 223         plat->interface = PHY_INTERFACE_MODE_SGMII;
 224         return ehl_common_data(pdev, plat);
 225 }
 226 
 227 static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
 228         .setup = ehl_sgmii_data,
 229 };
 230 
 231 static int ehl_rgmii_data(struct pci_dev *pdev,
 232                           struct plat_stmmacenet_data *plat)
 233 {
 234         plat->bus_id = 1;
 235         plat->phy_addr = 0;
 236         plat->interface = PHY_INTERFACE_MODE_RGMII;
 237         return ehl_common_data(pdev, plat);
 238 }
 239 
 240 static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
 241         .setup = ehl_rgmii_data,
 242 };
 243 
 244 static int tgl_common_data(struct pci_dev *pdev,
 245                            struct plat_stmmacenet_data *plat)
 246 {
 247         int ret;
 248 
 249         plat->rx_queues_to_use = 6;
 250         plat->tx_queues_to_use = 4;
 251         plat->clk_ptp_rate = 200000000;
 252         ret = intel_mgbe_common_data(pdev, plat);
 253         if (ret)
 254                 return ret;
 255 
 256         return 0;
 257 }
 258 
 259 static int tgl_sgmii_data(struct pci_dev *pdev,
 260                           struct plat_stmmacenet_data *plat)
 261 {
 262         plat->bus_id = 1;
 263         plat->phy_addr = 0;
 264         plat->interface = PHY_INTERFACE_MODE_SGMII;
 265         return tgl_common_data(pdev, plat);
 266 }
 267 
 268 static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
 269         .setup = tgl_sgmii_data,
 270 };
 271 
 272 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
 273         {
 274                 .func = 6,
 275                 .phy_addr = 1,
 276         },
 277 };
 278 
 279 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
 280         .func = galileo_stmmac_func_data,
 281         .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
 282 };
 283 
 284 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
 285         {
 286                 .func = 6,
 287                 .phy_addr = 1,
 288         },
 289         {
 290                 .func = 7,
 291                 .phy_addr = 1,
 292         },
 293 };
 294 
 295 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
 296         .func = iot2040_stmmac_func_data,
 297         .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
 298 };
 299 
 300 static const struct dmi_system_id quark_pci_dmi[] = {
 301         {
 302                 .matches = {
 303                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
 304                 },
 305                 .driver_data = (void *)&galileo_stmmac_dmi_data,
 306         },
 307         {
 308                 .matches = {
 309                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
 310                 },
 311                 .driver_data = (void *)&galileo_stmmac_dmi_data,
 312         },
 313         /*
 314          * There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
 315          * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
 316          * has only one pci network device while other asset tags are
 317          * for IOT2040 which has two.
 318          */
 319         {
 320                 .matches = {
 321                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
 322                         DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
 323                                         "6ES7647-0AA00-0YA2"),
 324                 },
 325                 .driver_data = (void *)&galileo_stmmac_dmi_data,
 326         },
 327         {
 328                 .matches = {
 329                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
 330                 },
 331                 .driver_data = (void *)&iot2040_stmmac_dmi_data,
 332         },
 333         {}
 334 };
 335 
 336 static int quark_default_data(struct pci_dev *pdev,
 337                               struct plat_stmmacenet_data *plat)
 338 {
 339         int ret;
 340 
 341         /* Set common default data first */
 342         common_default_data(plat);
 343 
 344         /*
 345          * Refuse to load the driver and register net device if MAC controller
 346          * does not connect to any PHY interface.
 347          */
 348         ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
 349         if (ret < 0) {
 350                 /* Return error to the caller on DMI enabled boards. */
 351                 if (dmi_get_system_info(DMI_BOARD_NAME))
 352                         return ret;
 353 
 354                 /*
 355                  * Galileo boards with old firmware don't support DMI. We always
 356                  * use 1 here as PHY address, so at least the first found MAC
 357                  * controller would be probed.
 358                  */
 359                 ret = 1;
 360         }
 361 
 362         plat->bus_id = pci_dev_id(pdev);
 363         plat->phy_addr = ret;
 364         plat->interface = PHY_INTERFACE_MODE_RMII;
 365 
 366         plat->dma_cfg->pbl = 16;
 367         plat->dma_cfg->pblx8 = true;
 368         plat->dma_cfg->fixed_burst = 1;
 369         /* AXI (TODO) */
 370 
 371         return 0;
 372 }
 373 
 374 static const struct stmmac_pci_info quark_pci_info = {
 375         .setup = quark_default_data,
 376 };
 377 
 378 static int snps_gmac5_default_data(struct pci_dev *pdev,
 379                                    struct plat_stmmacenet_data *plat)
 380 {
 381         int i;
 382 
 383         plat->clk_csr = 5;
 384         plat->has_gmac4 = 1;
 385         plat->force_sf_dma_mode = 1;
 386         plat->tso_en = 1;
 387         plat->pmt = 1;
 388 
 389         plat->mdio_bus_data->phy_mask = 0;
 390 
 391         /* Set default value for multicast hash bins */
 392         plat->multicast_filter_bins = HASH_TABLE_SIZE;
 393 
 394         /* Set default value for unicast filter entries */
 395         plat->unicast_filter_entries = 1;
 396 
 397         /* Set the maxmtu to a default of JUMBO_LEN */
 398         plat->maxmtu = JUMBO_LEN;
 399 
 400         /* Set default number of RX and TX queues to use */
 401         plat->tx_queues_to_use = 4;
 402         plat->rx_queues_to_use = 4;
 403 
 404         plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
 405         for (i = 0; i < plat->tx_queues_to_use; i++) {
 406                 plat->tx_queues_cfg[i].use_prio = false;
 407                 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
 408                 plat->tx_queues_cfg[i].weight = 25;
 409         }
 410 
 411         plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
 412         for (i = 0; i < plat->rx_queues_to_use; i++) {
 413                 plat->rx_queues_cfg[i].use_prio = false;
 414                 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
 415                 plat->rx_queues_cfg[i].pkt_route = 0x0;
 416                 plat->rx_queues_cfg[i].chan = i;
 417         }
 418 
 419         plat->bus_id = 1;
 420         plat->phy_addr = -1;
 421         plat->interface = PHY_INTERFACE_MODE_GMII;
 422 
 423         plat->dma_cfg->pbl = 32;
 424         plat->dma_cfg->pblx8 = true;
 425 
 426         /* Axi Configuration */
 427         plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), GFP_KERNEL);
 428         if (!plat->axi)
 429                 return -ENOMEM;
 430 
 431         plat->axi->axi_wr_osr_lmt = 31;
 432         plat->axi->axi_rd_osr_lmt = 31;
 433 
 434         plat->axi->axi_fb = false;
 435         plat->axi->axi_blen[0] = 4;
 436         plat->axi->axi_blen[1] = 8;
 437         plat->axi->axi_blen[2] = 16;
 438         plat->axi->axi_blen[3] = 32;
 439 
 440         return 0;
 441 }
 442 
 443 static const struct stmmac_pci_info snps_gmac5_pci_info = {
 444         .setup = snps_gmac5_default_data,
 445 };
 446 
 447 /**
 448  * stmmac_pci_probe
 449  *
 450  * @pdev: pci device pointer
 451  * @id: pointer to table of device id/id's.
 452  *
 453  * Description: This probing function gets called for all PCI devices which
 454  * match the ID table and are not "owned" by other driver yet. This function
 455  * gets passed a "struct pci_dev *" for each device whose entry in the ID table
 456  * matches the device. The probe functions returns zero when the driver choose
 457  * to take "ownership" of the device or an error code(-ve no) otherwise.
 458  */
 459 static int stmmac_pci_probe(struct pci_dev *pdev,
 460                             const struct pci_device_id *id)
 461 {
 462         struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
 463         struct plat_stmmacenet_data *plat;
 464         struct stmmac_resources res;
 465         int i;
 466         int ret;
 467 
 468         plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
 469         if (!plat)
 470                 return -ENOMEM;
 471 
 472         plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
 473                                            sizeof(*plat->mdio_bus_data),
 474                                            GFP_KERNEL);
 475         if (!plat->mdio_bus_data)
 476                 return -ENOMEM;
 477 
 478         plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
 479                                      GFP_KERNEL);
 480         if (!plat->dma_cfg)
 481                 return -ENOMEM;
 482 
 483         /* Enable pci device */
 484         ret = pci_enable_device(pdev);
 485         if (ret) {
 486                 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
 487                         __func__);
 488                 return ret;
 489         }
 490 
 491         /* Get the base address of device */
 492         for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
 493                 if (pci_resource_len(pdev, i) == 0)
 494                         continue;
 495                 ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev));
 496                 if (ret)
 497                         return ret;
 498                 break;
 499         }
 500 
 501         pci_set_master(pdev);
 502 
 503         ret = info->setup(pdev, plat);
 504         if (ret)
 505                 return ret;
 506 
 507         pci_enable_msi(pdev);
 508 
 509         memset(&res, 0, sizeof(res));
 510         res.addr = pcim_iomap_table(pdev)[i];
 511         res.wol_irq = pdev->irq;
 512         res.irq = pdev->irq;
 513 
 514         return stmmac_dvr_probe(&pdev->dev, plat, &res);
 515 }
 516 
 517 /**
 518  * stmmac_pci_remove
 519  *
 520  * @pdev: platform device pointer
 521  * Description: this function calls the main to free the net resources
 522  * and releases the PCI resources.
 523  */
 524 static void stmmac_pci_remove(struct pci_dev *pdev)
 525 {
 526         struct net_device *ndev = dev_get_drvdata(&pdev->dev);
 527         struct stmmac_priv *priv = netdev_priv(ndev);
 528         int i;
 529 
 530         stmmac_dvr_remove(&pdev->dev);
 531 
 532         if (priv->plat->stmmac_clk)
 533                 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
 534 
 535         for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
 536                 if (pci_resource_len(pdev, i) == 0)
 537                         continue;
 538                 pcim_iounmap_regions(pdev, BIT(i));
 539                 break;
 540         }
 541 
 542         pci_disable_device(pdev);
 543 }
 544 
 545 static int __maybe_unused stmmac_pci_suspend(struct device *dev)
 546 {
 547         struct pci_dev *pdev = to_pci_dev(dev);
 548         int ret;
 549 
 550         ret = stmmac_suspend(dev);
 551         if (ret)
 552                 return ret;
 553 
 554         ret = pci_save_state(pdev);
 555         if (ret)
 556                 return ret;
 557 
 558         pci_disable_device(pdev);
 559         pci_wake_from_d3(pdev, true);
 560         return 0;
 561 }
 562 
 563 static int __maybe_unused stmmac_pci_resume(struct device *dev)
 564 {
 565         struct pci_dev *pdev = to_pci_dev(dev);
 566         int ret;
 567 
 568         pci_restore_state(pdev);
 569         pci_set_power_state(pdev, PCI_D0);
 570 
 571         ret = pci_enable_device(pdev);
 572         if (ret)
 573                 return ret;
 574 
 575         pci_set_master(pdev);
 576 
 577         return stmmac_resume(dev);
 578 }
 579 
 580 static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume);
 581 
 582 /* synthetic ID, no official vendor */
 583 #define PCI_VENDOR_ID_STMMAC 0x700
 584 
 585 #define STMMAC_QUARK_ID  0x0937
 586 #define STMMAC_DEVICE_ID 0x1108
 587 #define STMMAC_EHL_RGMII1G_ID   0x4b30
 588 #define STMMAC_EHL_SGMII1G_ID   0x4b31
 589 #define STMMAC_TGL_SGMII1G_ID   0xa0ac
 590 #define STMMAC_GMAC5_ID         0x7102
 591 
 592 #define STMMAC_DEVICE(vendor_id, dev_id, info)  {       \
 593         PCI_VDEVICE(vendor_id, dev_id),                 \
 594         .driver_data = (kernel_ulong_t)&info            \
 595         }
 596 
 597 static const struct pci_device_id stmmac_id_table[] = {
 598         STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info),
 599         STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info),
 600         STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info),
 601         STMMAC_DEVICE(INTEL, STMMAC_EHL_RGMII1G_ID, ehl_rgmii1g_pci_info),
 602         STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info),
 603         STMMAC_DEVICE(INTEL, STMMAC_TGL_SGMII1G_ID, tgl_sgmii1g_pci_info),
 604         STMMAC_DEVICE(SYNOPSYS, STMMAC_GMAC5_ID, snps_gmac5_pci_info),
 605         {}
 606 };
 607 
 608 MODULE_DEVICE_TABLE(pci, stmmac_id_table);
 609 
 610 static struct pci_driver stmmac_pci_driver = {
 611         .name = STMMAC_RESOURCE_NAME,
 612         .id_table = stmmac_id_table,
 613         .probe = stmmac_pci_probe,
 614         .remove = stmmac_pci_remove,
 615         .driver         = {
 616                 .pm     = &stmmac_pm_ops,
 617         },
 618 };
 619 
 620 module_pci_driver(stmmac_pci_driver);
 621 
 622 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet PCI driver");
 623 MODULE_AUTHOR("Rayagond Kokatanur <rayagond.kokatanur@vayavyalabs.com>");
 624 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
 625 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c

DEFINITIONS
