This source file includes following definitions.
- rtsx_pci_get_cmd_data
- rtsx_pci_update_cfg_byte
- rtsx_pci_write_be32
- rtsx_pci_update_phy
1
2
3
4
5
6
7
8
9
10 #ifndef __RTSX_PCI_H
11 #define __RTSX_PCI_H
12
13 #include <linux/sched.h>
14 #include <linux/pci.h>
15 #include <linux/rtsx_common.h>
16
17 #define MAX_RW_REG_CNT 1024
18
19 #define RTSX_HCBAR 0x00
20 #define RTSX_HCBCTLR 0x04
21 #define STOP_CMD (0x01 << 28)
22 #define READ_REG_CMD 0
23 #define WRITE_REG_CMD 1
24 #define CHECK_REG_CMD 2
25
26 #define RTSX_HDBAR 0x08
27 #define RTSX_SG_INT 0x04
28 #define RTSX_SG_END 0x02
29 #define RTSX_SG_VALID 0x01
30 #define RTSX_SG_NO_OP 0x00
31 #define RTSX_SG_TRANS_DATA (0x02 << 4)
32 #define RTSX_SG_LINK_DESC (0x03 << 4)
33 #define RTSX_HDBCTLR 0x0C
34 #define SDMA_MODE 0x00
35 #define ADMA_MODE (0x02 << 26)
36 #define STOP_DMA (0x01 << 28)
37 #define TRIG_DMA (0x01 << 31)
38
39 #define RTSX_HAIMR 0x10
40 #define HAIMR_TRANS_START (0x01 << 31)
41 #define HAIMR_READ 0x00
42 #define HAIMR_WRITE (0x01 << 30)
43 #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
44 #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
45 #define HAIMR_TRANS_END (HAIMR_TRANS_START)
46
47 #define RTSX_BIPR 0x14
48 #define CMD_DONE_INT (1 << 31)
49 #define DATA_DONE_INT (1 << 30)
50 #define TRANS_OK_INT (1 << 29)
51 #define TRANS_FAIL_INT (1 << 28)
52 #define XD_INT (1 << 27)
53 #define MS_INT (1 << 26)
54 #define SD_INT (1 << 25)
55 #define GPIO0_INT (1 << 24)
56 #define OC_INT (1 << 23)
57 #define SD_WRITE_PROTECT (1 << 19)
58 #define XD_EXIST (1 << 18)
59 #define MS_EXIST (1 << 17)
60 #define SD_EXIST (1 << 16)
61 #define DELINK_INT GPIO0_INT
62 #define MS_OC_INT (1 << 23)
63 #define SD_OC_INT (1 << 22)
64
65 #define CARD_INT (XD_INT | MS_INT | SD_INT)
66 #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
67 #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
68 CARD_INT | GPIO0_INT | OC_INT)
69 #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
70
71 #define RTSX_BIER 0x18
72 #define CMD_DONE_INT_EN (1 << 31)
73 #define DATA_DONE_INT_EN (1 << 30)
74 #define TRANS_OK_INT_EN (1 << 29)
75 #define TRANS_FAIL_INT_EN (1 << 28)
76 #define XD_INT_EN (1 << 27)
77 #define MS_INT_EN (1 << 26)
78 #define SD_INT_EN (1 << 25)
79 #define GPIO0_INT_EN (1 << 24)
80 #define OC_INT_EN (1 << 23)
81 #define DELINK_INT_EN GPIO0_INT_EN
82 #define MS_OC_INT_EN (1 << 23)
83 #define SD_OC_INT_EN (1 << 22)
84
85
86
87
88
89 #define rtsx_pci_writel(pcr, reg, value) \
90 iowrite32(value, (pcr)->remap_addr + reg)
91 #define rtsx_pci_readl(pcr, reg) \
92 ioread32((pcr)->remap_addr + reg)
93 #define rtsx_pci_writew(pcr, reg, value) \
94 iowrite16(value, (pcr)->remap_addr + reg)
95 #define rtsx_pci_readw(pcr, reg) \
96 ioread16((pcr)->remap_addr + reg)
97 #define rtsx_pci_writeb(pcr, reg, value) \
98 iowrite8(value, (pcr)->remap_addr + reg)
99 #define rtsx_pci_readb(pcr, reg) \
100 ioread8((pcr)->remap_addr + reg)
101
102 #define rtsx_pci_read_config_byte(pcr, where, val) \
103 pci_read_config_byte((pcr)->pci, where, val)
104
105 #define rtsx_pci_write_config_byte(pcr, where, val) \
106 pci_write_config_byte((pcr)->pci, where, val)
107
108 #define rtsx_pci_read_config_dword(pcr, where, val) \
109 pci_read_config_dword((pcr)->pci, where, val)
110
111 #define rtsx_pci_write_config_dword(pcr, where, val) \
112 pci_write_config_dword((pcr)->pci, where, val)
113
114 #define STATE_TRANS_NONE 0
115 #define STATE_TRANS_CMD 1
116 #define STATE_TRANS_BUF 2
117 #define STATE_TRANS_SG 3
118
119 #define TRANS_NOT_READY 0
120 #define TRANS_RESULT_OK 1
121 #define TRANS_RESULT_FAIL 2
122 #define TRANS_NO_DEVICE 3
123
124 #define RTSX_RESV_BUF_LEN 4096
125 #define HOST_CMDS_BUF_LEN 1024
126 #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
127 #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
128 #define MAX_SG_ITEM_LEN 0x80000
129 #define HOST_TO_DEVICE 0
130 #define DEVICE_TO_HOST 1
131
132 #define OUTPUT_3V3 0
133 #define OUTPUT_1V8 1
134
135 #define RTSX_PHASE_MAX 32
136 #define RX_TUNING_CNT 3
137
138 #define MS_CFG 0xFD40
139 #define SAMPLE_TIME_RISING 0x00
140 #define SAMPLE_TIME_FALLING 0x80
141 #define PUSH_TIME_DEFAULT 0x00
142 #define PUSH_TIME_ODD 0x40
143 #define NO_EXTEND_TOGGLE 0x00
144 #define EXTEND_TOGGLE_CHK 0x20
145 #define MS_BUS_WIDTH_1 0x00
146 #define MS_BUS_WIDTH_4 0x10
147 #define MS_BUS_WIDTH_8 0x18
148 #define MS_2K_SECTOR_MODE 0x04
149 #define MS_512_SECTOR_MODE 0x00
150 #define MS_TOGGLE_TIMEOUT_EN 0x00
151 #define MS_TOGGLE_TIMEOUT_DISEN 0x01
152 #define MS_NO_CHECK_INT 0x02
153 #define MS_TPC 0xFD41
154 #define MS_TRANS_CFG 0xFD42
155 #define WAIT_INT 0x80
156 #define NO_WAIT_INT 0x00
157 #define NO_AUTO_READ_INT_REG 0x00
158 #define AUTO_READ_INT_REG 0x40
159 #define MS_CRC16_ERR 0x20
160 #define MS_RDY_TIMEOUT 0x10
161 #define MS_INT_CMDNK 0x08
162 #define MS_INT_BREQ 0x04
163 #define MS_INT_ERR 0x02
164 #define MS_INT_CED 0x01
165 #define MS_TRANSFER 0xFD43
166 #define MS_TRANSFER_START 0x80
167 #define MS_TRANSFER_END 0x40
168 #define MS_TRANSFER_ERR 0x20
169 #define MS_BS_STATE 0x10
170 #define MS_TM_READ_BYTES 0x00
171 #define MS_TM_NORMAL_READ 0x01
172 #define MS_TM_WRITE_BYTES 0x04
173 #define MS_TM_NORMAL_WRITE 0x05
174 #define MS_TM_AUTO_READ 0x08
175 #define MS_TM_AUTO_WRITE 0x0C
176 #define MS_INT_REG 0xFD44
177 #define MS_BYTE_CNT 0xFD45
178 #define MS_SECTOR_CNT_L 0xFD46
179 #define MS_SECTOR_CNT_H 0xFD47
180 #define MS_DBUS_H 0xFD48
181
182 #define SD_CFG1 0xFDA0
183 #define SD_CLK_DIVIDE_0 0x00
184 #define SD_CLK_DIVIDE_256 0xC0
185 #define SD_CLK_DIVIDE_128 0x80
186 #define SD_BUS_WIDTH_1BIT 0x00
187 #define SD_BUS_WIDTH_4BIT 0x01
188 #define SD_BUS_WIDTH_8BIT 0x02
189 #define SD_ASYNC_FIFO_NOT_RST 0x10
190 #define SD_20_MODE 0x00
191 #define SD_DDR_MODE 0x04
192 #define SD_30_MODE 0x08
193 #define SD_CLK_DIVIDE_MASK 0xC0
194 #define SD_MODE_SELECT_MASK 0x0C
195 #define SD_CFG2 0xFDA1
196 #define SD_CALCULATE_CRC7 0x00
197 #define SD_NO_CALCULATE_CRC7 0x80
198 #define SD_CHECK_CRC16 0x00
199 #define SD_NO_CHECK_CRC16 0x40
200 #define SD_NO_CHECK_WAIT_CRC_TO 0x20
201 #define SD_WAIT_BUSY_END 0x08
202 #define SD_NO_WAIT_BUSY_END 0x00
203 #define SD_CHECK_CRC7 0x00
204 #define SD_NO_CHECK_CRC7 0x04
205 #define SD_RSP_LEN_0 0x00
206 #define SD_RSP_LEN_6 0x01
207 #define SD_RSP_LEN_17 0x02
208 #define SD_RSP_TYPE_R0 0x04
209 #define SD_RSP_TYPE_R1 0x01
210 #define SD_RSP_TYPE_R1b 0x09
211 #define SD_RSP_TYPE_R2 0x02
212 #define SD_RSP_TYPE_R3 0x05
213 #define SD_RSP_TYPE_R4 0x05
214 #define SD_RSP_TYPE_R5 0x01
215 #define SD_RSP_TYPE_R6 0x01
216 #define SD_RSP_TYPE_R7 0x01
217 #define SD_CFG3 0xFDA2
218 #define SD30_CLK_END_EN 0x10
219 #define SD_RSP_80CLK_TIMEOUT_EN 0x01
220
221 #define SD_STAT1 0xFDA3
222 #define SD_CRC7_ERR 0x80
223 #define SD_CRC16_ERR 0x40
224 #define SD_CRC_WRITE_ERR 0x20
225 #define SD_CRC_WRITE_ERR_MASK 0x1C
226 #define GET_CRC_TIME_OUT 0x02
227 #define SD_TUNING_COMPARE_ERR 0x01
228 #define SD_STAT2 0xFDA4
229 #define SD_RSP_80CLK_TIMEOUT 0x01
230
231 #define SD_BUS_STAT 0xFDA5
232 #define SD_CLK_TOGGLE_EN 0x80
233 #define SD_CLK_FORCE_STOP 0x40
234 #define SD_DAT3_STATUS 0x10
235 #define SD_DAT2_STATUS 0x08
236 #define SD_DAT1_STATUS 0x04
237 #define SD_DAT0_STATUS 0x02
238 #define SD_CMD_STATUS 0x01
239 #define SD_PAD_CTL 0xFDA6
240 #define SD_IO_USING_1V8 0x80
241 #define SD_IO_USING_3V3 0x7F
242 #define TYPE_A_DRIVING 0x00
243 #define TYPE_B_DRIVING 0x01
244 #define TYPE_C_DRIVING 0x02
245 #define TYPE_D_DRIVING 0x03
246 #define SD_SAMPLE_POINT_CTL 0xFDA7
247 #define DDR_FIX_RX_DAT 0x00
248 #define DDR_VAR_RX_DAT 0x80
249 #define DDR_FIX_RX_DAT_EDGE 0x00
250 #define DDR_FIX_RX_DAT_14_DELAY 0x40
251 #define DDR_FIX_RX_CMD 0x00
252 #define DDR_VAR_RX_CMD 0x20
253 #define DDR_FIX_RX_CMD_POS_EDGE 0x00
254 #define DDR_FIX_RX_CMD_14_DELAY 0x10
255 #define SD20_RX_POS_EDGE 0x00
256 #define SD20_RX_14_DELAY 0x08
257 #define SD20_RX_SEL_MASK 0x08
258 #define SD_PUSH_POINT_CTL 0xFDA8
259 #define DDR_FIX_TX_CMD_DAT 0x00
260 #define DDR_VAR_TX_CMD_DAT 0x80
261 #define DDR_FIX_TX_DAT_14_TSU 0x00
262 #define DDR_FIX_TX_DAT_12_TSU 0x40
263 #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
264 #define DDR_FIX_TX_CMD_14_AHEAD 0x20
265 #define SD20_TX_NEG_EDGE 0x00
266 #define SD20_TX_14_AHEAD 0x10
267 #define SD20_TX_SEL_MASK 0x10
268 #define DDR_VAR_SDCLK_POL_SWAP 0x01
269 #define SD_CMD0 0xFDA9
270 #define SD_CMD_START 0x40
271 #define SD_CMD1 0xFDAA
272 #define SD_CMD2 0xFDAB
273 #define SD_CMD3 0xFDAC
274 #define SD_CMD4 0xFDAD
275 #define SD_CMD5 0xFDAE
276 #define SD_BYTE_CNT_L 0xFDAF
277 #define SD_BYTE_CNT_H 0xFDB0
278 #define SD_BLOCK_CNT_L 0xFDB1
279 #define SD_BLOCK_CNT_H 0xFDB2
280 #define SD_TRANSFER 0xFDB3
281 #define SD_TRANSFER_START 0x80
282 #define SD_TRANSFER_END 0x40
283 #define SD_STAT_IDLE 0x20
284 #define SD_TRANSFER_ERR 0x10
285 #define SD_TM_NORMAL_WRITE 0x00
286 #define SD_TM_AUTO_WRITE_3 0x01
287 #define SD_TM_AUTO_WRITE_4 0x02
288 #define SD_TM_AUTO_READ_3 0x05
289 #define SD_TM_AUTO_READ_4 0x06
290 #define SD_TM_CMD_RSP 0x08
291 #define SD_TM_AUTO_WRITE_1 0x09
292 #define SD_TM_AUTO_WRITE_2 0x0A
293 #define SD_TM_NORMAL_READ 0x0C
294 #define SD_TM_AUTO_READ_1 0x0D
295 #define SD_TM_AUTO_READ_2 0x0E
296 #define SD_TM_AUTO_TUNING 0x0F
297 #define SD_CMD_STATE 0xFDB5
298 #define SD_CMD_IDLE 0x80
299
300 #define SD_DATA_STATE 0xFDB6
301 #define SD_DATA_IDLE 0x80
302 #define REG_SD_STOP_SDCLK_CFG 0xFDB8
303 #define SD30_CLK_STOP_CFG_EN 0x04
304 #define SD30_CLK_STOP_CFG1 0x02
305 #define SD30_CLK_STOP_CFG0 0x01
306 #define REG_PRE_RW_MODE 0xFD70
307 #define EN_INFINITE_MODE 0x01
308
309 #define SRCTL 0xFC13
310
311 #define DCM_DRP_CTL 0xFC23
312 #define DCM_RESET 0x08
313 #define DCM_LOCKED 0x04
314 #define DCM_208M 0x00
315 #define DCM_TX 0x01
316 #define DCM_RX 0x02
317 #define DCM_DRP_TRIG 0xFC24
318 #define DRP_START 0x80
319 #define DRP_DONE 0x40
320 #define DCM_DRP_CFG 0xFC25
321 #define DRP_WRITE 0x80
322 #define DRP_READ 0x00
323 #define DCM_WRITE_ADDRESS_50 0x50
324 #define DCM_WRITE_ADDRESS_51 0x51
325 #define DCM_READ_ADDRESS_00 0x00
326 #define DCM_READ_ADDRESS_51 0x51
327 #define DCM_DRP_WR_DATA_L 0xFC26
328 #define DCM_DRP_WR_DATA_H 0xFC27
329 #define DCM_DRP_RD_DATA_L 0xFC28
330 #define DCM_DRP_RD_DATA_H 0xFC29
331 #define SD_VPCLK0_CTL 0xFC2A
332 #define SD_VPCLK1_CTL 0xFC2B
333 #define PHASE_SELECT_MASK 0x1F
334 #define SD_DCMPS0_CTL 0xFC2C
335 #define SD_DCMPS1_CTL 0xFC2D
336 #define SD_VPTX_CTL SD_VPCLK0_CTL
337 #define SD_VPRX_CTL SD_VPCLK1_CTL
338 #define PHASE_CHANGE 0x80
339 #define PHASE_NOT_RESET 0x40
340 #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
341 #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
342 #define DCMPS_CHANGE 0x80
343 #define DCMPS_CHANGE_DONE 0x40
344 #define DCMPS_ERROR 0x20
345 #define DCMPS_CURRENT_PHASE 0x1F
346 #define CARD_CLK_SOURCE 0xFC2E
347 #define CRC_FIX_CLK (0x00 << 0)
348 #define CRC_VAR_CLK0 (0x01 << 0)
349 #define CRC_VAR_CLK1 (0x02 << 0)
350 #define SD30_FIX_CLK (0x00 << 2)
351 #define SD30_VAR_CLK0 (0x01 << 2)
352 #define SD30_VAR_CLK1 (0x02 << 2)
353 #define SAMPLE_FIX_CLK (0x00 << 4)
354 #define SAMPLE_VAR_CLK0 (0x01 << 4)
355 #define SAMPLE_VAR_CLK1 (0x02 << 4)
356 #define CARD_PWR_CTL 0xFD50
357 #define PMOS_STRG_MASK 0x10
358 #define PMOS_STRG_800mA 0x10
359 #define PMOS_STRG_400mA 0x00
360 #define SD_POWER_OFF 0x03
361 #define SD_PARTIAL_POWER_ON 0x01
362 #define SD_POWER_ON 0x00
363 #define SD_POWER_MASK 0x03
364 #define MS_POWER_OFF 0x0C
365 #define MS_PARTIAL_POWER_ON 0x04
366 #define MS_POWER_ON 0x00
367 #define MS_POWER_MASK 0x0C
368 #define BPP_POWER_OFF 0x0F
369 #define BPP_POWER_5_PERCENT_ON 0x0E
370 #define BPP_POWER_10_PERCENT_ON 0x0C
371 #define BPP_POWER_15_PERCENT_ON 0x08
372 #define BPP_POWER_ON 0x00
373 #define BPP_POWER_MASK 0x0F
374 #define SD_VCC_PARTIAL_POWER_ON 0x02
375 #define SD_VCC_POWER_ON 0x00
376 #define CARD_CLK_SWITCH 0xFD51
377 #define RTL8411B_PACKAGE_MODE 0xFD51
378 #define CARD_SHARE_MODE 0xFD52
379 #define CARD_SHARE_MASK 0x0F
380 #define CARD_SHARE_MULTI_LUN 0x00
381 #define CARD_SHARE_NORMAL 0x00
382 #define CARD_SHARE_48_SD 0x04
383 #define CARD_SHARE_48_MS 0x08
384 #define CARD_SHARE_BAROSSA_SD 0x01
385 #define CARD_SHARE_BAROSSA_MS 0x02
386 #define CARD_DRIVE_SEL 0xFD53
387 #define MS_DRIVE_8mA (0x01 << 6)
388 #define MMC_DRIVE_8mA (0x01 << 4)
389 #define XD_DRIVE_8mA (0x01 << 2)
390 #define GPIO_DRIVE_8mA 0x01
391 #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
392 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
393 #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
394 XD_DRIVE_8mA)
395 #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
396
397 #define CARD_STOP 0xFD54
398 #define SPI_STOP 0x01
399 #define XD_STOP 0x02
400 #define SD_STOP 0x04
401 #define MS_STOP 0x08
402 #define SPI_CLR_ERR 0x10
403 #define XD_CLR_ERR 0x20
404 #define SD_CLR_ERR 0x40
405 #define MS_CLR_ERR 0x80
406 #define CARD_OE 0xFD55
407 #define SD_OUTPUT_EN 0x04
408 #define MS_OUTPUT_EN 0x08
409 #define CARD_AUTO_BLINK 0xFD56
410 #define CARD_GPIO_DIR 0xFD57
411 #define CARD_GPIO 0xFD58
412 #define CARD_DATA_SOURCE 0xFD5B
413 #define PINGPONG_BUFFER 0x01
414 #define RING_BUFFER 0x00
415 #define SD30_CLK_DRIVE_SEL 0xFD5A
416 #define DRIVER_TYPE_A 0x05
417 #define DRIVER_TYPE_B 0x03
418 #define DRIVER_TYPE_C 0x02
419 #define DRIVER_TYPE_D 0x01
420 #define CARD_SELECT 0xFD5C
421 #define SD_MOD_SEL 2
422 #define MS_MOD_SEL 3
423 #define SD30_DRIVE_SEL 0xFD5E
424 #define CFG_DRIVER_TYPE_A 0x02
425 #define CFG_DRIVER_TYPE_B 0x03
426 #define CFG_DRIVER_TYPE_C 0x01
427 #define CFG_DRIVER_TYPE_D 0x00
428 #define SD30_CMD_DRIVE_SEL 0xFD5E
429 #define SD30_DAT_DRIVE_SEL 0xFD5F
430 #define CARD_CLK_EN 0xFD69
431 #define SD_CLK_EN 0x04
432 #define MS_CLK_EN 0x08
433 #define SD40_CLK_EN 0x10
434 #define SDIO_CTRL 0xFD6B
435 #define CD_PAD_CTL 0xFD73
436 #define CD_DISABLE_MASK 0x07
437 #define MS_CD_DISABLE 0x04
438 #define SD_CD_DISABLE 0x02
439 #define XD_CD_DISABLE 0x01
440 #define CD_DISABLE 0x07
441 #define CD_ENABLE 0x00
442 #define MS_CD_EN_ONLY 0x03
443 #define SD_CD_EN_ONLY 0x05
444 #define XD_CD_EN_ONLY 0x06
445 #define FORCE_CD_LOW_MASK 0x38
446 #define FORCE_CD_XD_LOW 0x08
447 #define FORCE_CD_SD_LOW 0x10
448 #define FORCE_CD_MS_LOW 0x20
449 #define CD_AUTO_DISABLE 0x40
450 #define FPDCTL 0xFC00
451 #define SSC_POWER_DOWN 0x01
452 #define SD_OC_POWER_DOWN 0x02
453 #define ALL_POWER_DOWN 0x03
454 #define OC_POWER_DOWN 0x02
455 #define PDINFO 0xFC01
456
457 #define CLK_CTL 0xFC02
458 #define CHANGE_CLK 0x01
459 #define CLK_LOW_FREQ 0x01
460
461 #define CLK_DIV 0xFC03
462 #define CLK_DIV_1 0x01
463 #define CLK_DIV_2 0x02
464 #define CLK_DIV_4 0x03
465 #define CLK_DIV_8 0x04
466 #define CLK_SEL 0xFC04
467
468 #define SSC_DIV_N_0 0xFC0F
469 #define SSC_DIV_N_1 0xFC10
470 #define SSC_CTL1 0xFC11
471 #define SSC_RSTB 0x80
472 #define SSC_8X_EN 0x40
473 #define SSC_FIX_FRAC 0x20
474 #define SSC_SEL_1M 0x00
475 #define SSC_SEL_2M 0x08
476 #define SSC_SEL_4M 0x10
477 #define SSC_SEL_8M 0x18
478 #define SSC_CTL2 0xFC12
479 #define SSC_DEPTH_MASK 0x07
480 #define SSC_DEPTH_DISALBE 0x00
481 #define SSC_DEPTH_4M 0x01
482 #define SSC_DEPTH_2M 0x02
483 #define SSC_DEPTH_1M 0x03
484 #define SSC_DEPTH_500K 0x04
485 #define SSC_DEPTH_250K 0x05
486 #define RCCTL 0xFC14
487
488 #define FPGA_PULL_CTL 0xFC1D
489 #define OLT_LED_CTL 0xFC1E
490 #define LED_SHINE_MASK 0x08
491 #define LED_SHINE_EN 0x08
492 #define LED_SHINE_DISABLE 0x00
493 #define GPIO_CTL 0xFC1F
494
495 #define LDO_CTL 0xFC1E
496 #define BPP_ASIC_1V7 0x00
497 #define BPP_ASIC_1V8 0x01
498 #define BPP_ASIC_1V9 0x02
499 #define BPP_ASIC_2V0 0x03
500 #define BPP_ASIC_2V7 0x04
501 #define BPP_ASIC_2V8 0x05
502 #define BPP_ASIC_3V2 0x06
503 #define BPP_ASIC_3V3 0x07
504 #define BPP_REG_TUNED18 0x07
505 #define BPP_TUNED18_SHIFT_8402 5
506 #define BPP_TUNED18_SHIFT_8411 4
507 #define BPP_PAD_MASK 0x04
508 #define BPP_PAD_3V3 0x04
509 #define BPP_PAD_1V8 0x00
510 #define BPP_LDO_POWB 0x03
511 #define BPP_LDO_ON 0x00
512 #define BPP_LDO_SUSPEND 0x02
513 #define BPP_LDO_OFF 0x03
514 #define EFUSE_CTL 0xFC30
515 #define EFUSE_ADD 0xFC31
516 #define SYS_VER 0xFC32
517 #define EFUSE_DATAL 0xFC34
518 #define EFUSE_DATAH 0xFC35
519
520 #define CARD_PULL_CTL1 0xFD60
521 #define CARD_PULL_CTL2 0xFD61
522 #define CARD_PULL_CTL3 0xFD62
523 #define CARD_PULL_CTL4 0xFD63
524 #define CARD_PULL_CTL5 0xFD64
525 #define CARD_PULL_CTL6 0xFD65
526
527
528 #define IRQEN0 0xFE20
529 #define IRQSTAT0 0xFE21
530 #define DMA_DONE_INT 0x80
531 #define SUSPEND_INT 0x40
532 #define LINK_RDY_INT 0x20
533 #define LINK_DOWN_INT 0x10
534 #define IRQEN1 0xFE22
535 #define IRQSTAT1 0xFE23
536 #define TLPRIEN 0xFE24
537 #define TLPRISTAT 0xFE25
538 #define TLPTIEN 0xFE26
539 #define TLPTISTAT 0xFE27
540 #define DMATC0 0xFE28
541 #define DMATC1 0xFE29
542 #define DMATC2 0xFE2A
543 #define DMATC3 0xFE2B
544 #define DMACTL 0xFE2C
545 #define DMA_RST 0x80
546 #define DMA_BUSY 0x04
547 #define DMA_DIR_TO_CARD 0x00
548 #define DMA_DIR_FROM_CARD 0x02
549 #define DMA_EN 0x01
550 #define DMA_128 (0 << 4)
551 #define DMA_256 (1 << 4)
552 #define DMA_512 (2 << 4)
553 #define DMA_1024 (3 << 4)
554 #define DMA_PACK_SIZE_MASK 0x30
555 #define BCTL 0xFE2D
556 #define RBBC0 0xFE2E
557 #define RBBC1 0xFE2F
558 #define RBDAT 0xFE30
559 #define RBCTL 0xFE34
560 #define U_AUTO_DMA_EN_MASK 0x20
561 #define U_AUTO_DMA_DISABLE 0x00
562 #define RB_FLUSH 0x80
563 #define CFGADDR0 0xFE35
564 #define CFGADDR1 0xFE36
565 #define CFGDATA0 0xFE37
566 #define CFGDATA1 0xFE38
567 #define CFGDATA2 0xFE39
568 #define CFGDATA3 0xFE3A
569 #define CFGRWCTL 0xFE3B
570 #define PHYRWCTL 0xFE3C
571 #define PHYDATA0 0xFE3D
572 #define PHYDATA1 0xFE3E
573 #define PHYADDR 0xFE3F
574 #define MSGRXDATA0 0xFE40
575 #define MSGRXDATA1 0xFE41
576 #define MSGRXDATA2 0xFE42
577 #define MSGRXDATA3 0xFE43
578 #define MSGTXDATA0 0xFE44
579 #define MSGTXDATA1 0xFE45
580 #define MSGTXDATA2 0xFE46
581 #define MSGTXDATA3 0xFE47
582 #define MSGTXCTL 0xFE48
583 #define LTR_CTL 0xFE4A
584 #define LTR_TX_EN_MASK BIT(7)
585 #define LTR_TX_EN_1 BIT(7)
586 #define LTR_TX_EN_0 0
587 #define LTR_LATENCY_MODE_MASK BIT(6)
588 #define LTR_LATENCY_MODE_HW 0
589 #define LTR_LATENCY_MODE_SW BIT(6)
590 #define OBFF_CFG 0xFE4C
591 #define OBFF_EN_MASK 0x03
592 #define OBFF_DISABLE 0x00
593
594 #define CDRESUMECTL 0xFE52
595 #define WAKE_SEL_CTL 0xFE54
596 #define PCLK_CTL 0xFE55
597 #define PCLK_MODE_SEL 0x20
598 #define PME_FORCE_CTL 0xFE56
599
600 #define ASPM_FORCE_CTL 0xFE57
601 #define FORCE_ASPM_CTL0 0x10
602 #define FORCE_ASPM_VAL_MASK 0x03
603 #define FORCE_ASPM_L1_EN 0x02
604 #define FORCE_ASPM_L0_EN 0x01
605 #define FORCE_ASPM_NO_ASPM 0x00
606 #define PM_CLK_FORCE_CTL 0xFE58
607 #define CLK_PM_EN 0x01
608 #define FUNC_FORCE_CTL 0xFE59
609 #define FUNC_FORCE_UPME_XMT_DBG 0x02
610 #define PERST_GLITCH_WIDTH 0xFE5C
611 #define CHANGE_LINK_STATE 0xFE5B
612 #define RESET_LOAD_REG 0xFE5E
613 #define EFUSE_CONTENT 0xFE5F
614 #define HOST_SLEEP_STATE 0xFE60
615 #define HOST_ENTER_S1 1
616 #define HOST_ENTER_S3 2
617
618 #define SDIO_CFG 0xFE70
619 #define PM_EVENT_DEBUG 0xFE71
620 #define PME_DEBUG_0 0x08
621 #define NFTS_TX_CTRL 0xFE72
622
623 #define PWR_GATE_CTRL 0xFE75
624 #define PWR_GATE_EN 0x01
625 #define LDO3318_PWR_MASK 0x06
626 #define LDO_ON 0x00
627 #define LDO_SUSPEND 0x04
628 #define LDO_OFF 0x06
629 #define PWD_SUSPEND_EN 0xFE76
630 #define LDO_PWR_SEL 0xFE78
631
632 #define L1SUB_CONFIG1 0xFE8D
633 #define AUX_CLK_ACTIVE_SEL_MASK 0x01
634 #define MAC_CKSW_DONE 0x00
635 #define L1SUB_CONFIG2 0xFE8E
636 #define L1SUB_AUTO_CFG 0x02
637 #define L1SUB_CONFIG3 0xFE8F
638 #define L1OFF_MBIAS2_EN_5250 BIT(7)
639
640 #define DUMMY_REG_RESET_0 0xFE90
641 #define IC_VERSION_MASK 0x0F
642
643 #define REG_VREF 0xFE97
644 #define PWD_SUSPND_EN 0x10
645 #define RTS5260_DMA_RST_CTL_0 0xFEBF
646 #define RTS5260_DMA_RST 0x80
647 #define RTS5260_ADMA3_RST 0x40
648 #define AUTOLOAD_CFG_BASE 0xFF00
649 #define RELINK_TIME_MASK 0x01
650 #define PETXCFG 0xFF03
651 #define FORCE_CLKREQ_DELINK_MASK BIT(7)
652 #define FORCE_CLKREQ_LOW 0x80
653 #define FORCE_CLKREQ_HIGH 0x00
654
655 #define PM_CTRL1 0xFF44
656 #define CD_RESUME_EN_MASK 0xF0
657
658 #define PM_CTRL2 0xFF45
659 #define PM_CTRL3 0xFF46
660 #define SDIO_SEND_PME_EN 0x80
661 #define FORCE_RC_MODE_ON 0x40
662 #define FORCE_RX50_LINK_ON 0x20
663 #define D3_DELINK_MODE_EN 0x10
664 #define USE_PESRTB_CTL_DELINK 0x08
665 #define DELAY_PIN_WAKE 0x04
666 #define RESET_PIN_WAKE 0x02
667 #define PM_WAKE_EN 0x01
668 #define PM_CTRL4 0xFF47
669
670
671 #define SRAM_BASE 0xE600
672 #define RBUF_BASE 0xF400
673 #define PPBUF_BASE1 0xF800
674 #define PPBUF_BASE2 0xFA00
675 #define IMAGE_FLAG_ADDR0 0xCE80
676 #define IMAGE_FLAG_ADDR1 0xCE81
677
678 #define RREF_CFG 0xFF6C
679 #define RREF_VBGSEL_MASK 0x38
680 #define RREF_VBGSEL_1V25 0x28
681
682 #define OOBS_CONFIG 0xFF6E
683 #define OOBS_AUTOK_DIS 0x80
684 #define OOBS_VAL_MASK 0x1F
685
686 #define LDO_DV18_CFG 0xFF70
687 #define LDO_DV18_SR_MASK 0xC0
688 #define LDO_DV18_SR_DF 0x40
689 #define DV331812_MASK 0x70
690 #define DV331812_33 0x70
691 #define DV331812_17 0x30
692
693 #define LDO_CONFIG2 0xFF71
694 #define LDO_D3318_MASK 0x07
695 #define LDO_D3318_33V 0x07
696 #define LDO_D3318_18V 0x02
697 #define DV331812_VDD1 0x04
698 #define DV331812_POWERON 0x08
699 #define DV331812_POWEROFF 0x00
700
701 #define LDO_VCC_CFG0 0xFF72
702 #define LDO_VCC_LMTVTH_MASK 0x30
703 #define LDO_VCC_LMTVTH_2A 0x10
704
705 #define RTS5260_DVCC_TUNE_MASK 0x70
706 #define RTS5260_DVCC_33 0x70
707
708 #define LDO_VCC_CFG1 0xFF73
709 #define LDO_VCC_REF_TUNE_MASK 0x30
710 #define LDO_VCC_REF_1V2 0x20
711 #define LDO_VCC_TUNE_MASK 0x07
712 #define LDO_VCC_1V8 0x04
713 #define LDO_VCC_3V3 0x07
714 #define LDO_VCC_LMT_EN 0x08
715
716 #define LDO_POW_SDVDD1_MASK 0x08
717 #define LDO_POW_SDVDD1_ON 0x08
718 #define LDO_POW_SDVDD1_OFF 0x00
719
720 #define LDO_VIO_CFG 0xFF75
721 #define LDO_VIO_SR_MASK 0xC0
722 #define LDO_VIO_SR_DF 0x40
723 #define LDO_VIO_REF_TUNE_MASK 0x30
724 #define LDO_VIO_REF_1V2 0x20
725 #define LDO_VIO_TUNE_MASK 0x07
726 #define LDO_VIO_1V7 0x03
727 #define LDO_VIO_1V8 0x04
728 #define LDO_VIO_3V3 0x07
729
730 #define LDO_DV12S_CFG 0xFF76
731 #define LDO_REF12_TUNE_MASK 0x18
732 #define LDO_REF12_TUNE_DF 0x10
733 #define LDO_D12_TUNE_MASK 0x07
734 #define LDO_D12_TUNE_DF 0x04
735
736 #define LDO_AV12S_CFG 0xFF77
737 #define LDO_AV12S_TUNE_MASK 0x07
738 #define LDO_AV12S_TUNE_DF 0x04
739
740 #define SD40_LDO_CTL1 0xFE7D
741 #define SD40_VIO_TUNE_MASK 0x70
742 #define SD40_VIO_TUNE_1V7 0x30
743 #define SD_VIO_LDO_1V8 0x40
744 #define SD_VIO_LDO_3V3 0x70
745
746 #define RTS5260_AUTOLOAD_CFG4 0xFF7F
747 #define RTS5260_MIMO_DISABLE 0x8A
748
749 #define RTS5260_REG_GPIO_CTL0 0xFC1A
750 #define RTS5260_REG_GPIO_MASK 0x01
751 #define RTS5260_REG_GPIO_ON 0x01
752 #define RTS5260_REG_GPIO_OFF 0x00
753
754 #define PWR_GLOBAL_CTRL 0xF200
755 #define PCIE_L1_2_EN 0x0C
756 #define PCIE_L1_1_EN 0x0A
757 #define PCIE_L1_0_EN 0x09
758 #define PWR_FE_CTL 0xF201
759 #define PCIE_L1_2_PD_FE_EN 0x0C
760 #define PCIE_L1_1_PD_FE_EN 0x0A
761 #define PCIE_L1_0_PD_FE_EN 0x09
762 #define CFG_PCIE_APHY_OFF_0 0xF204
763 #define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF
764 #define CFG_PCIE_APHY_OFF_1 0xF205
765 #define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF
766 #define CFG_PCIE_APHY_OFF_2 0xF206
767 #define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01
768 #define CFG_PCIE_APHY_OFF_3 0xF207
769 #define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00
770 #define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C
771 #define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E
772 #define CFG_L1_0_SYS_RET_VALUE 0xF210
773 #define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212
774 #define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214
775 #define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216
776 #define CFG_LP_FPWM_VALUE 0xF219
777 #define CFG_LP_FPWM_VALUE_DEFAULT 0x18
778 #define PWC_CDR 0xF253
779 #define PWC_CDR_DEFAULT 0x03
780 #define CFG_L1_0_RET_VALUE_DEFAULT 0x1B
781 #define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C
782
783
784 #define SD_DETECT_EN 0x08
785 #define SD_OCP_INT_EN 0x04
786 #define SD_OCP_INT_CLR 0x02
787 #define SD_OC_CLR 0x01
788
789 #define SDVIO_DETECT_EN (1 << 7)
790 #define SDVIO_OCP_INT_EN (1 << 6)
791 #define SDVIO_OCP_INT_CLR (1 << 5)
792 #define SDVIO_OC_CLR (1 << 4)
793
794
795 #define SD_OCP_DETECT 0x08
796 #define SD_OC_NOW 0x04
797 #define SD_OC_EVER 0x02
798
799 #define SDVIO_OC_NOW (1 << 6)
800 #define SDVIO_OC_EVER (1 << 5)
801
802 #define REG_OCPCTL 0xFD6A
803 #define REG_OCPSTAT 0xFD6E
804 #define REG_OCPGLITCH 0xFD6C
805 #define REG_OCPPARA1 0xFD6B
806 #define REG_OCPPARA2 0xFD6D
807
808
809 #define REG_DV3318_OCPCTL 0xFD89
810 #define DV3318_OCP_TIME_MASK 0xF0
811 #define DV3318_DETECT_EN 0x08
812 #define DV3318_OCP_INT_EN 0x04
813 #define DV3318_OCP_INT_CLR 0x02
814 #define DV3318_OCP_CLR 0x01
815
816 #define REG_DV3318_OCPSTAT 0xFD8A
817 #define DV3318_OCP_GlITCH_TIME_MASK 0xF0
818 #define DV3318_OCP_DETECT 0x08
819 #define DV3318_OCP_NOW 0x04
820 #define DV3318_OCP_EVER 0x02
821
822 #define SD_OCP_GLITCH_MASK 0x0F
823
824
825 #define SDVIO_OCP_TIME_60 0x00
826 #define SDVIO_OCP_TIME_100 0x10
827 #define SDVIO_OCP_TIME_200 0x20
828 #define SDVIO_OCP_TIME_400 0x30
829 #define SDVIO_OCP_TIME_600 0x40
830 #define SDVIO_OCP_TIME_800 0x50
831 #define SDVIO_OCP_TIME_1100 0x60
832 #define SDVIO_OCP_TIME_MASK 0x70
833
834 #define SD_OCP_TIME_60 0x00
835 #define SD_OCP_TIME_100 0x01
836 #define SD_OCP_TIME_200 0x02
837 #define SD_OCP_TIME_400 0x03
838 #define SD_OCP_TIME_600 0x04
839 #define SD_OCP_TIME_800 0x05
840 #define SD_OCP_TIME_1100 0x06
841 #define SD_OCP_TIME_MASK 0x07
842
843
844 #define SDVIO_OCP_THD_190 0x00
845 #define SDVIO_OCP_THD_250 0x10
846 #define SDVIO_OCP_THD_320 0x20
847 #define SDVIO_OCP_THD_380 0x30
848 #define SDVIO_OCP_THD_440 0x40
849 #define SDVIO_OCP_THD_500 0x50
850 #define SDVIO_OCP_THD_570 0x60
851 #define SDVIO_OCP_THD_630 0x70
852 #define SDVIO_OCP_THD_MASK 0x70
853
854 #define SD_OCP_THD_450 0x00
855 #define SD_OCP_THD_550 0x01
856 #define SD_OCP_THD_650 0x02
857 #define SD_OCP_THD_750 0x03
858 #define SD_OCP_THD_850 0x04
859 #define SD_OCP_THD_950 0x05
860 #define SD_OCP_THD_1050 0x06
861 #define SD_OCP_THD_1150 0x07
862 #define SD_OCP_THD_MASK 0x07
863
864 #define SDVIO_OCP_GLITCH_MASK 0xF0
865 #define SDVIO_OCP_GLITCH_NONE 0x00
866 #define SDVIO_OCP_GLITCH_50U 0x10
867 #define SDVIO_OCP_GLITCH_100U 0x20
868 #define SDVIO_OCP_GLITCH_200U 0x30
869 #define SDVIO_OCP_GLITCH_600U 0x40
870 #define SDVIO_OCP_GLITCH_800U 0x50
871 #define SDVIO_OCP_GLITCH_1M 0x60
872 #define SDVIO_OCP_GLITCH_2M 0x70
873 #define SDVIO_OCP_GLITCH_3M 0x80
874 #define SDVIO_OCP_GLITCH_4M 0x90
875 #define SDVIO_OCP_GLIVCH_5M 0xA0
876 #define SDVIO_OCP_GLITCH_6M 0xB0
877 #define SDVIO_OCP_GLITCH_7M 0xC0
878 #define SDVIO_OCP_GLITCH_8M 0xD0
879 #define SDVIO_OCP_GLITCH_9M 0xE0
880 #define SDVIO_OCP_GLITCH_10M 0xF0
881
882 #define SD_OCP_GLITCH_MASK 0x0F
883 #define SD_OCP_GLITCH_NONE 0x00
884 #define SD_OCP_GLITCH_50U 0x01
885 #define SD_OCP_GLITCH_100U 0x02
886 #define SD_OCP_GLITCH_200U 0x03
887 #define SD_OCP_GLITCH_600U 0x04
888 #define SD_OCP_GLITCH_800U 0x05
889 #define SD_OCP_GLITCH_1M 0x06
890 #define SD_OCP_GLITCH_2M 0x07
891 #define SD_OCP_GLITCH_3M 0x08
892 #define SD_OCP_GLITCH_4M 0x09
893 #define SD_OCP_GLIVCH_5M 0x0A
894 #define SD_OCP_GLITCH_6M 0x0B
895 #define SD_OCP_GLITCH_7M 0x0C
896 #define SD_OCP_GLITCH_8M 0x0D
897 #define SD_OCP_GLITCH_9M 0x0E
898 #define SD_OCP_GLITCH_10M 0x0F
899
900
901 #define PHY_PCR 0x00
902 #define PHY_PCR_FORCE_CODE 0xB000
903 #define PHY_PCR_OOBS_CALI_50 0x0800
904 #define PHY_PCR_OOBS_VCM_08 0x0200
905 #define PHY_PCR_OOBS_SEN_90 0x0040
906 #define PHY_PCR_RSSI_EN 0x0002
907 #define PHY_PCR_RX10K 0x0001
908
909 #define PHY_RCR0 0x01
910 #define PHY_RCR1 0x02
911 #define PHY_RCR1_ADP_TIME_4 0x0400
912 #define PHY_RCR1_VCO_COARSE 0x001F
913 #define PHY_RCR1_INIT_27S 0x0A1F
914 #define PHY_SSCCR2 0x02
915 #define PHY_SSCCR2_PLL_NCODE 0x0A00
916 #define PHY_SSCCR2_TIME0 0x001C
917 #define PHY_SSCCR2_TIME2_WIDTH 0x0003
918
919 #define PHY_RCR2 0x03
920 #define PHY_RCR2_EMPHASE_EN 0x8000
921 #define PHY_RCR2_NADJR 0x4000
922 #define PHY_RCR2_CDR_SR_2 0x0100
923 #define PHY_RCR2_FREQSEL_12 0x0040
924 #define PHY_RCR2_CDR_SC_12P 0x0010
925 #define PHY_RCR2_CALIB_LATE 0x0002
926 #define PHY_RCR2_INIT_27S 0xC152
927 #define PHY_SSCCR3 0x03
928 #define PHY_SSCCR3_STEP_IN 0x2740
929 #define PHY_SSCCR3_CHECK_DELAY 0x0008
930 #define _PHY_ANA03 0x03
931 #define _PHY_ANA03_TIMER_MAX 0x2700
932 #define _PHY_ANA03_OOBS_DEB_EN 0x0040
933 #define _PHY_CMU_DEBUG_EN 0x0008
934
935 #define PHY_RTCR 0x04
936 #define PHY_RDR 0x05
937 #define PHY_RDR_RXDSEL_1_9 0x4000
938 #define PHY_SSC_AUTO_PWD 0x0600
939 #define PHY_TCR0 0x06
940 #define PHY_TCR1 0x07
941 #define PHY_TUNE 0x08
942 #define PHY_TUNE_TUNEREF_1_0 0x4000
943 #define PHY_TUNE_VBGSEL_1252 0x0C00
944 #define PHY_TUNE_SDBUS_33 0x0200
945 #define PHY_TUNE_TUNED18 0x01C0
946 #define PHY_TUNE_TUNED12 0X0020
947 #define PHY_TUNE_TUNEA12 0x0004
948 #define PHY_TUNE_VOLTAGE_MASK 0xFC3F
949 #define PHY_TUNE_VOLTAGE_3V3 0x03C0
950 #define PHY_TUNE_D18_1V8 0x0100
951 #define PHY_TUNE_D18_1V7 0x0080
952 #define PHY_ANA08 0x08
953 #define PHY_ANA08_RX_EQ_DCGAIN 0x5000
954 #define PHY_ANA08_SEL_RX_EN 0x0400
955 #define PHY_ANA08_RX_EQ_VAL 0x03C0
956 #define PHY_ANA08_SCP 0x0020
957 #define PHY_ANA08_SEL_IPI 0x0004
958
959 #define PHY_IMR 0x09
960 #define PHY_BPCR 0x0A
961 #define PHY_BPCR_IBRXSEL 0x0400
962 #define PHY_BPCR_IBTXSEL 0x0100
963 #define PHY_BPCR_IB_FILTER 0x0080
964 #define PHY_BPCR_CMIRROR_EN 0x0040
965
966 #define PHY_BIST 0x0B
967 #define PHY_RAW_L 0x0C
968 #define PHY_RAW_H 0x0D
969 #define PHY_RAW_DATA 0x0E
970 #define PHY_HOST_CLK_CTRL 0x0F
971 #define PHY_DMR 0x10
972 #define PHY_BACR 0x11
973 #define PHY_BACR_BASIC_MASK 0xFFF3
974 #define PHY_IER 0x12
975 #define PHY_BCSR 0x13
976 #define PHY_BPR 0x14
977 #define PHY_BPNR2 0x15
978 #define PHY_BPNR 0x16
979 #define PHY_BRNR2 0x17
980 #define PHY_BENR 0x18
981 #define PHY_REV 0x19
982 #define PHY_REV_RESV 0xE000
983 #define PHY_REV_RXIDLE_LATCHED 0x1000
984 #define PHY_REV_P1_EN 0x0800
985 #define PHY_REV_RXIDLE_EN 0x0400
986 #define PHY_REV_CLKREQ_TX_EN 0x0200
987 #define PHY_REV_CLKREQ_RX_EN 0x0100
988 #define PHY_REV_CLKREQ_DT_1_0 0x0040
989 #define PHY_REV_STOP_CLKRD 0x0020
990 #define PHY_REV_RX_PWST 0x0008
991 #define PHY_REV_STOP_CLKWR 0x0004
992 #define _PHY_REV0 0x19
993 #define _PHY_REV0_FILTER_OUT 0x3800
994 #define _PHY_REV0_CDR_BYPASS_PFD 0x0100
995 #define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002
996
997 #define PHY_FLD0 0x1A
998 #define PHY_ANA1A 0x1A
999 #define PHY_ANA1A_TXR_LOOPBACK 0x2000
1000 #define PHY_ANA1A_RXT_BIST 0x0500
1001 #define PHY_ANA1A_TXR_BIST 0x0040
1002 #define PHY_ANA1A_REV 0x0006
1003 #define PHY_FLD0_INIT_27S 0x2546
1004 #define PHY_FLD1 0x1B
1005 #define PHY_FLD2 0x1C
1006 #define PHY_FLD3 0x1D
1007 #define PHY_FLD3_TIMER_4 0x0800
1008 #define PHY_FLD3_TIMER_6 0x0020
1009 #define PHY_FLD3_RXDELINK 0x0004
1010 #define PHY_FLD3_INIT_27S 0x0004
1011 #define PHY_ANA1D 0x1D
1012 #define PHY_ANA1D_DEBUG_ADDR 0x0004
1013 #define _PHY_FLD0 0x1D
1014 #define _PHY_FLD0_CLK_REQ_20C 0x8000
1015 #define _PHY_FLD0_RX_IDLE_EN 0x1000
1016 #define _PHY_FLD0_BIT_ERR_RSTN 0x0800
1017 #define _PHY_FLD0_BER_COUNT 0x01E0
1018 #define _PHY_FLD0_BER_TIMER 0x001E
1019 #define _PHY_FLD0_CHECK_EN 0x0001
1020
1021 #define PHY_FLD4 0x1E
1022 #define PHY_FLD4_FLDEN_SEL 0x4000
1023 #define PHY_FLD4_REQ_REF 0x2000
1024 #define PHY_FLD4_RXAMP_OFF 0x1000
1025 #define PHY_FLD4_REQ_ADDA 0x0800
1026 #define PHY_FLD4_BER_COUNT 0x00E0
1027 #define PHY_FLD4_BER_TIMER 0x000A
1028 #define PHY_FLD4_BER_CHK_EN 0x0001
1029 #define PHY_FLD4_INIT_27S 0x5C7F
1030 #define PHY_DIG1E 0x1E
1031 #define PHY_DIG1E_REV 0x4000
1032 #define PHY_DIG1E_D0_X_D1 0x1000
1033 #define PHY_DIG1E_RX_ON_HOST 0x0800
1034 #define PHY_DIG1E_RCLK_REF_HOST 0x0400
1035 #define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040
1036 #define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020
1037 #define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010
1038 #define PHY_DIG1E_TX_TERM_KEEP 0x0008
1039 #define PHY_DIG1E_RX_TERM_KEEP 0x0004
1040 #define PHY_DIG1E_TX_EN_KEEP 0x0002
1041 #define PHY_DIG1E_RX_EN_KEEP 0x0001
1042 #define PHY_DUM_REG 0x1F
1043
1044 #define PCR_ASPM_SETTING_REG1 0x160
1045 #define PCR_ASPM_SETTING_REG2 0x168
1046 #define PCR_ASPM_SETTING_5260 0x178
1047
1048 #define PCR_SETTING_REG1 0x724
1049 #define PCR_SETTING_REG2 0x814
1050 #define PCR_SETTING_REG3 0x747
1051
1052 #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
1053
1054 #define RTS5227_DEVICE_ID 0x5227
1055 #define RTS_MAX_TIMES_FREQ_REDUCTION 8
1056
1057 struct rtsx_pcr;
1058
1059 struct pcr_handle {
1060 struct rtsx_pcr *pcr;
1061 };
1062
1063 struct pcr_ops {
1064 int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
1065 int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1066 int (*extra_init_hw)(struct rtsx_pcr *pcr);
1067 int (*optimize_phy)(struct rtsx_pcr *pcr);
1068 int (*turn_on_led)(struct rtsx_pcr *pcr);
1069 int (*turn_off_led)(struct rtsx_pcr *pcr);
1070 int (*enable_auto_blink)(struct rtsx_pcr *pcr);
1071 int (*disable_auto_blink)(struct rtsx_pcr *pcr);
1072 int (*card_power_on)(struct rtsx_pcr *pcr, int card);
1073 int (*card_power_off)(struct rtsx_pcr *pcr, int card);
1074 int (*switch_output_voltage)(struct rtsx_pcr *pcr,
1075 u8 voltage);
1076 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
1077 int (*conv_clk_and_div_n)(int clk, int dir);
1078 void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
1079 void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
1080 void (*stop_cmd)(struct rtsx_pcr *pcr);
1081
1082 void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
1083 int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
1084 int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
1085 void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
1086 void (*full_on)(struct rtsx_pcr *pcr);
1087 void (*power_saving)(struct rtsx_pcr *pcr);
1088 void (*enable_ocp)(struct rtsx_pcr *pcr);
1089 void (*disable_ocp)(struct rtsx_pcr *pcr);
1090 void (*init_ocp)(struct rtsx_pcr *pcr);
1091 void (*process_ocp)(struct rtsx_pcr *pcr);
1092 int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
1093 void (*clear_ocpstat)(struct rtsx_pcr *pcr);
1094 };
1095
1096 enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
1097
1098 #define ASPM_L1_1_EN_MASK BIT(3)
1099 #define ASPM_L1_2_EN_MASK BIT(2)
1100 #define PM_L1_1_EN_MASK BIT(1)
1101 #define PM_L1_2_EN_MASK BIT(0)
1102
1103 #define ASPM_L1_1_EN BIT(0)
1104 #define ASPM_L1_2_EN BIT(1)
1105 #define PM_L1_1_EN BIT(2)
1106 #define PM_L1_2_EN BIT(3)
1107 #define LTR_L1SS_PWR_GATE_EN BIT(4)
1108 #define L1_SNOOZE_TEST_EN BIT(5)
1109 #define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6)
1110
1111 enum dev_aspm_mode {
1112 DEV_ASPM_DYNAMIC,
1113 DEV_ASPM_BACKDOOR,
1114 DEV_ASPM_STATIC,
1115 DEV_ASPM_DISABLE,
1116 };
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136 struct rtsx_cr_option {
1137 u32 dev_flags;
1138 bool force_clkreq_0;
1139 bool ltr_en;
1140 bool ltr_enabled;
1141 bool ltr_active;
1142 u32 ltr_active_latency;
1143 u32 ltr_idle_latency;
1144 u32 ltr_l1off_latency;
1145 enum dev_aspm_mode dev_aspm_mode;
1146 u32 l1_snooze_delay;
1147 u8 ltr_l1off_sspwrgate;
1148 u8 ltr_l1off_snooze_sspwrgate;
1149 bool ocp_en;
1150 u8 sd_400mA_ocp_thd;
1151 u8 sd_800mA_ocp_thd;
1152 };
1153
1154
1155
1156
1157
1158
1159 struct rtsx_hw_param {
1160 u32 interrupt_en;
1161 u8 ocp_glitch;
1162 };
1163
1164 #define rtsx_set_dev_flag(cr, flag) \
1165 ((cr)->option.dev_flags |= (flag))
1166 #define rtsx_clear_dev_flag(cr, flag) \
1167 ((cr)->option.dev_flags &= ~(flag))
1168 #define rtsx_check_dev_flag(cr, flag) \
1169 ((cr)->option.dev_flags & (flag))
1170
1171 struct rtsx_pcr {
1172 struct pci_dev *pci;
1173 unsigned int id;
1174 int pcie_cap;
1175 struct rtsx_cr_option option;
1176 struct rtsx_hw_param hw_param;
1177
1178
1179 unsigned long addr;
1180 void __iomem *remap_addr;
1181 int irq;
1182
1183
1184 void *rtsx_resv_buf;
1185 dma_addr_t rtsx_resv_buf_addr;
1186
1187 void *host_cmds_ptr;
1188 dma_addr_t host_cmds_addr;
1189 int ci;
1190
1191 void *host_sg_tbl_ptr;
1192 dma_addr_t host_sg_tbl_addr;
1193 int sgi;
1194
1195 u32 bier;
1196 char trans_result;
1197
1198 unsigned int card_inserted;
1199 unsigned int card_removed;
1200 unsigned int card_exist;
1201
1202 struct delayed_work carddet_work;
1203 struct delayed_work idle_work;
1204
1205 spinlock_t lock;
1206 struct mutex pcr_mutex;
1207 struct completion *done;
1208 struct completion *finish_me;
1209
1210 unsigned int cur_clock;
1211 bool remove_pci;
1212 bool msi_en;
1213
1214 #define EXTRA_CAPS_SD_SDR50 (1 << 0)
1215 #define EXTRA_CAPS_SD_SDR104 (1 << 1)
1216 #define EXTRA_CAPS_SD_DDR50 (1 << 2)
1217 #define EXTRA_CAPS_MMC_HSDDR (1 << 3)
1218 #define EXTRA_CAPS_MMC_HS200 (1 << 4)
1219 #define EXTRA_CAPS_MMC_8BIT (1 << 5)
1220 u32 extra_caps;
1221
1222 #define IC_VER_A 0
1223 #define IC_VER_B 1
1224 #define IC_VER_C 2
1225 #define IC_VER_D 3
1226 u8 ic_version;
1227
1228 u8 sd30_drive_sel_1v8;
1229 u8 sd30_drive_sel_3v3;
1230 u8 card_drive_sel;
1231 #define ASPM_L1_EN 0x02
1232 u8 aspm_en;
1233 bool aspm_enabled;
1234
1235 #define PCR_MS_PMOS (1 << 0)
1236 #define PCR_REVERSE_SOCKET (1 << 1)
1237 u32 flags;
1238
1239 u32 tx_initial_phase;
1240 u32 rx_initial_phase;
1241
1242 const u32 *sd_pull_ctl_enable_tbl;
1243 const u32 *sd_pull_ctl_disable_tbl;
1244 const u32 *ms_pull_ctl_enable_tbl;
1245 const u32 *ms_pull_ctl_disable_tbl;
1246
1247 const struct pcr_ops *ops;
1248 enum PDEV_STAT state;
1249
1250 u16 reg_pm_ctrl3;
1251
1252 int num_slots;
1253 struct rtsx_slot *slots;
1254
1255 u8 dma_error_count;
1256 u8 ocp_stat;
1257 u8 ocp_stat2;
1258 };
1259
1260 #define PID_524A 0x524A
1261 #define PID_5249 0x5249
1262 #define PID_5250 0x5250
1263 #define PID_525A 0x525A
1264 #define PID_5260 0x5260
1265
1266 #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
1267 #define PCI_VID(pcr) ((pcr)->pci->vendor)
1268 #define PCI_PID(pcr) ((pcr)->pci->device)
1269 #define is_version(pcr, pid, ver) \
1270 (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
1271 #define pcr_dbg(pcr, fmt, arg...) \
1272 dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
1273
1274 #define SDR104_PHASE(val) ((val) & 0xFF)
1275 #define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
1276 #define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
1277 #define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
1278 #define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
1279 #define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
1280 #define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
1281 #define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
1282 #define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
1283 #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
1284 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
1285
1286 void rtsx_pci_start_run(struct rtsx_pcr *pcr);
1287 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
1288 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
1289 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
1290 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1291 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
1292 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1293 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
1294 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
1295 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
1296 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1297 int num_sg, bool read, int timeout);
1298 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1299 int num_sg, bool read);
1300 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1301 int num_sg, bool read);
1302 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1303 int count, bool read, int timeout);
1304 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1305 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1306 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
1307 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
1308 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
1309 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
1310 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
1311 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
1312 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
1313 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
1314 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
1315 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
1316
1317 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
1318 {
1319 return (u8 *)(pcr->host_cmds_ptr);
1320 }
1321
1322 static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
1323 u8 mask, u8 append)
1324 {
1325 int err;
1326 u8 val;
1327
1328 err = pci_read_config_byte(pcr->pci, addr, &val);
1329 if (err < 0)
1330 return err;
1331 return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
1332 }
1333
1334 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
1335 {
1336 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24);
1337 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
1338 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
1339 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
1340 }
1341
1342 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
1343 u16 mask, u16 append)
1344 {
1345 int err;
1346 u16 val;
1347
1348 err = rtsx_pci_read_phy_register(pcr, addr, &val);
1349 if (err < 0)
1350 return err;
1351
1352 return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
1353 }
1354
1355 #endif