1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Driver for the Synopsys DesignWare DMA Controller
4 *
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
7 */
8 #ifndef _PLATFORM_DATA_DMA_DW_H
9 #define _PLATFORM_DATA_DMA_DW_H
10
11 #include <linux/device.h>
12
13 #define DW_DMA_MAX_NR_MASTERS 4
14 #define DW_DMA_MAX_NR_CHANNELS 8
15
16 /**
17 * struct dw_dma_slave - Controller-specific information about a slave
18 *
19 * @dma_dev: required DMA master device
20 * @src_id: src request line
21 * @dst_id: dst request line
22 * @m_master: memory master for transfers on allocated channel
23 * @p_master: peripheral master for transfers on allocated channel
24 * @hs_polarity:set active low polarity of handshake interface
25 */
26 struct dw_dma_slave {
27 struct device *dma_dev;
28 u8 src_id;
29 u8 dst_id;
30 u8 m_master;
31 u8 p_master;
32 bool hs_polarity;
33 };
34
35 /**
36 * struct dw_dma_platform_data - Controller configuration parameters
37 * @nr_channels: Number of channels supported by hardware (max 8)
38 * @chan_allocation_order: Allocate channels starting from 0 or 7
39 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
40 * @block_size: Maximum block size supported by the controller
41 * @nr_masters: Number of AHB masters supported by the controller
42 * @data_width: Maximum data width supported by hardware per AHB master
43 * (in bytes, power of 2)
44 * @multi_block: Multi block transfers supported by hardware per channel.
45 * @protctl: Protection control signals setting per channel.
46 */
47 struct dw_dma_platform_data {
48 unsigned int nr_channels;
49 #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
50 #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
51 unsigned char chan_allocation_order;
52 #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
53 #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
54 unsigned char chan_priority;
55 unsigned int block_size;
56 unsigned char nr_masters;
57 unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
58 unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
59 #define CHAN_PROTCTL_PRIVILEGED BIT(0)
60 #define CHAN_PROTCTL_BUFFERABLE BIT(1)
61 #define CHAN_PROTCTL_CACHEABLE BIT(2)
62 #define CHAN_PROTCTL_MASK GENMASK(2, 0)
63 unsigned char protctl;
64 };
65
66 #endif /* _PLATFORM_DATA_DMA_DW_H */