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  43 #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
  44 #define _DT_BINDINGS_CLK_SUN50I_A64_H_
  45 
  46 #define CLK_PLL_VIDEO0          7
  47 #define CLK_PLL_PERIPH0         11
  48 
  49 #define CLK_BUS_MIPI_DSI        28
  50 #define CLK_BUS_CE              29
  51 #define CLK_BUS_DMA             30
  52 #define CLK_BUS_MMC0            31
  53 #define CLK_BUS_MMC1            32
  54 #define CLK_BUS_MMC2            33
  55 #define CLK_BUS_NAND            34
  56 #define CLK_BUS_DRAM            35
  57 #define CLK_BUS_EMAC            36
  58 #define CLK_BUS_TS              37
  59 #define CLK_BUS_HSTIMER         38
  60 #define CLK_BUS_SPI0            39
  61 #define CLK_BUS_SPI1            40
  62 #define CLK_BUS_OTG             41
  63 #define CLK_BUS_EHCI0           42
  64 #define CLK_BUS_EHCI1           43
  65 #define CLK_BUS_OHCI0           44
  66 #define CLK_BUS_OHCI1           45
  67 #define CLK_BUS_VE              46
  68 #define CLK_BUS_TCON0           47
  69 #define CLK_BUS_TCON1           48
  70 #define CLK_BUS_DEINTERLACE     49
  71 #define CLK_BUS_CSI             50
  72 #define CLK_BUS_HDMI            51
  73 #define CLK_BUS_DE              52
  74 #define CLK_BUS_GPU             53
  75 #define CLK_BUS_MSGBOX          54
  76 #define CLK_BUS_SPINLOCK        55
  77 #define CLK_BUS_CODEC           56
  78 #define CLK_BUS_SPDIF           57
  79 #define CLK_BUS_PIO             58
  80 #define CLK_BUS_THS             59
  81 #define CLK_BUS_I2S0            60
  82 #define CLK_BUS_I2S1            61
  83 #define CLK_BUS_I2S2            62
  84 #define CLK_BUS_I2C0            63
  85 #define CLK_BUS_I2C1            64
  86 #define CLK_BUS_I2C2            65
  87 #define CLK_BUS_SCR             66
  88 #define CLK_BUS_UART0           67
  89 #define CLK_BUS_UART1           68
  90 #define CLK_BUS_UART2           69
  91 #define CLK_BUS_UART3           70
  92 #define CLK_BUS_UART4           71
  93 #define CLK_BUS_DBG             72
  94 #define CLK_THS                 73
  95 #define CLK_NAND                74
  96 #define CLK_MMC0                75
  97 #define CLK_MMC1                76
  98 #define CLK_MMC2                77
  99 #define CLK_TS                  78
 100 #define CLK_CE                  79
 101 #define CLK_SPI0                80
 102 #define CLK_SPI1                81
 103 #define CLK_I2S0                82
 104 #define CLK_I2S1                83
 105 #define CLK_I2S2                84
 106 #define CLK_SPDIF               85
 107 #define CLK_USB_PHY0            86
 108 #define CLK_USB_PHY1            87
 109 #define CLK_USB_HSIC            88
 110 #define CLK_USB_HSIC_12M        89
 111 
 112 #define CLK_USB_OHCI0           91
 113 
 114 #define CLK_USB_OHCI1           93
 115 
 116 #define CLK_DRAM_VE             95
 117 #define CLK_DRAM_CSI            96
 118 #define CLK_DRAM_DEINTERLACE    97
 119 #define CLK_DRAM_TS             98
 120 #define CLK_DE                  99
 121 #define CLK_TCON0               100
 122 #define CLK_TCON1               101
 123 #define CLK_DEINTERLACE         102
 124 #define CLK_CSI_MISC            103
 125 #define CLK_CSI_SCLK            104
 126 #define CLK_CSI_MCLK            105
 127 #define CLK_VE                  106
 128 #define CLK_AC_DIG              107
 129 #define CLK_AC_DIG_4X           108
 130 #define CLK_AVS                 109
 131 #define CLK_HDMI                110
 132 #define CLK_HDMI_DDC            111
 133 
 134 #define CLK_DSI_DPHY            113
 135 #define CLK_GPU                 114
 136 
 137 #endif