1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /*
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * Copyright(c) 2015 Intel Corporation.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
22 * Copyright(c) 2015 Intel Corporation.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * - Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * - Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * - Neither the name of Intel Corporation nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 */
51
52 #ifndef _LINUX__HFI1_IOCTL_H
53 #define _LINUX__HFI1_IOCTL_H
54 #include <linux/types.h>
55
56 /*
57 * This structure is passed to the driver to tell it where
58 * user code buffers are, sizes, etc. The offsets and sizes of the
59 * fields must remain unchanged, for binary compatibility. It can
60 * be extended, if userversion is changed so user code can tell, if needed
61 */
62 struct hfi1_user_info {
63 /*
64 * version of user software, to detect compatibility issues.
65 * Should be set to HFI1_USER_SWVERSION.
66 */
67 __u32 userversion;
68 __u32 pad;
69 /*
70 * If two or more processes wish to share a context, each process
71 * must set the subcontext_cnt and subcontext_id to the same
72 * values. The only restriction on the subcontext_id is that
73 * it be unique for a given node.
74 */
75 __u16 subctxt_cnt;
76 __u16 subctxt_id;
77 /* 128bit UUID passed in by PSM. */
78 __u8 uuid[16];
79 };
80
81 struct hfi1_ctxt_info {
82 __aligned_u64 runtime_flags; /* chip/drv runtime flags (HFI1_CAP_*) */
83 __u32 rcvegr_size; /* size of each eager buffer */
84 __u16 num_active; /* number of active units */
85 __u16 unit; /* unit (chip) assigned to caller */
86 __u16 ctxt; /* ctxt on unit assigned to caller */
87 __u16 subctxt; /* subctxt on unit assigned to caller */
88 __u16 rcvtids; /* number of Rcv TIDs for this context */
89 __u16 credits; /* number of PIO credits for this context */
90 __u16 numa_node; /* NUMA node of the assigned device */
91 __u16 rec_cpu; /* cpu # for affinity (0xffff if none) */
92 __u16 send_ctxt; /* send context in use by this user context */
93 __u16 egrtids; /* number of RcvArray entries for Eager Rcvs */
94 __u16 rcvhdrq_cnt; /* number of RcvHdrQ entries */
95 __u16 rcvhdrq_entsize; /* size (in bytes) for each RcvHdrQ entry */
96 __u16 sdma_ring_size; /* number of entries in SDMA request ring */
97 };
98
99 struct hfi1_tid_info {
100 /* virtual address of first page in transfer */
101 __aligned_u64 vaddr;
102 /* pointer to tid array. this array is big enough */
103 __aligned_u64 tidlist;
104 /* number of tids programmed by this request */
105 __u32 tidcnt;
106 /* length of transfer buffer programmed by this request */
107 __u32 length;
108 };
109
110 /*
111 * This structure is returned by the driver immediately after
112 * open to get implementation-specific info, and info specific to this
113 * instance.
114 *
115 * This struct must have explicit pad fields where type sizes
116 * may result in different alignments between 32 and 64 bit
117 * programs, since the 64 bit * bit kernel requires the user code
118 * to have matching offsets
119 */
120 struct hfi1_base_info {
121 /* version of hardware, for feature checking. */
122 __u32 hw_version;
123 /* version of software, for feature checking. */
124 __u32 sw_version;
125 /* Job key */
126 __u16 jkey;
127 __u16 padding1;
128 /*
129 * The special QP (queue pair) value that identifies PSM
130 * protocol packet from standard IB packets.
131 */
132 __u32 bthqp;
133 /* PIO credit return address, */
134 __aligned_u64 sc_credits_addr;
135 /*
136 * Base address of write-only pio buffers for this process.
137 * Each buffer has sendpio_credits*64 bytes.
138 */
139 __aligned_u64 pio_bufbase_sop;
140 /*
141 * Base address of write-only pio buffers for this process.
142 * Each buffer has sendpio_credits*64 bytes.
143 */
144 __aligned_u64 pio_bufbase;
145 /* address where receive buffer queue is mapped into */
146 __aligned_u64 rcvhdr_bufbase;
147 /* base address of Eager receive buffers. */
148 __aligned_u64 rcvegr_bufbase;
149 /* base address of SDMA completion ring */
150 __aligned_u64 sdma_comp_bufbase;
151 /*
152 * User register base for init code, not to be used directly by
153 * protocol or applications. Always maps real chip register space.
154 * the register addresses are:
155 * ur_rcvhdrhead, ur_rcvhdrtail, ur_rcvegrhead, ur_rcvegrtail,
156 * ur_rcvtidflow
157 */
158 __aligned_u64 user_regbase;
159 /* notification events */
160 __aligned_u64 events_bufbase;
161 /* status page */
162 __aligned_u64 status_bufbase;
163 /* rcvhdrtail update */
164 __aligned_u64 rcvhdrtail_base;
165 /*
166 * shared memory pages for subctxts if ctxt is shared; these cover
167 * all the processes in the group sharing a single context.
168 * all have enough space for the num_subcontexts value on this job.
169 */
170 __aligned_u64 subctxt_uregbase;
171 __aligned_u64 subctxt_rcvegrbuf;
172 __aligned_u64 subctxt_rcvhdrbuf;
173 };
174 #endif /* _LINIUX__HFI1_IOCTL_H */