root/include/uapi/drm/lima_drm.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
   2 /* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
   3 
   4 #ifndef __LIMA_DRM_H__
   5 #define __LIMA_DRM_H__
   6 
   7 #include "drm.h"
   8 
   9 #if defined(__cplusplus)
  10 extern "C" {
  11 #endif
  12 
  13 enum drm_lima_param_gpu_id {
  14         DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
  15         DRM_LIMA_PARAM_GPU_ID_MALI400,
  16         DRM_LIMA_PARAM_GPU_ID_MALI450,
  17 };
  18 
  19 enum drm_lima_param {
  20         DRM_LIMA_PARAM_GPU_ID,
  21         DRM_LIMA_PARAM_NUM_PP,
  22         DRM_LIMA_PARAM_GP_VERSION,
  23         DRM_LIMA_PARAM_PP_VERSION,
  24 };
  25 
  26 /**
  27  * get various information of the GPU
  28  */
  29 struct drm_lima_get_param {
  30         __u32 param; /* in, value in enum drm_lima_param */
  31         __u32 pad;   /* pad, must be zero */
  32         __u64 value; /* out, parameter value */
  33 };
  34 
  35 /**
  36  * create a buffer for used by GPU
  37  */
  38 struct drm_lima_gem_create {
  39         __u32 size;    /* in, buffer size */
  40         __u32 flags;   /* in, currently no flags, must be zero */
  41         __u32 handle;  /* out, GEM buffer handle */
  42         __u32 pad;     /* pad, must be zero */
  43 };
  44 
  45 /**
  46  * get information of a buffer
  47  */
  48 struct drm_lima_gem_info {
  49         __u32 handle;  /* in, GEM buffer handle */
  50         __u32 va;      /* out, virtual address mapped into GPU MMU */
  51         __u64 offset;  /* out, used to mmap this buffer to CPU */
  52 };
  53 
  54 #define LIMA_SUBMIT_BO_READ   0x01
  55 #define LIMA_SUBMIT_BO_WRITE  0x02
  56 
  57 /* buffer information used by one task */
  58 struct drm_lima_gem_submit_bo {
  59         __u32 handle;  /* in, GEM buffer handle */
  60         __u32 flags;   /* in, buffer read/write by GPU */
  61 };
  62 
  63 #define LIMA_GP_FRAME_REG_NUM 6
  64 
  65 /* frame used to setup GP for each task */
  66 struct drm_lima_gp_frame {
  67         __u32 frame[LIMA_GP_FRAME_REG_NUM];
  68 };
  69 
  70 #define LIMA_PP_FRAME_REG_NUM 23
  71 #define LIMA_PP_WB_REG_NUM 12
  72 
  73 /* frame used to setup mali400 GPU PP for each task */
  74 struct drm_lima_m400_pp_frame {
  75         __u32 frame[LIMA_PP_FRAME_REG_NUM];
  76         __u32 num_pp;
  77         __u32 wb[3 * LIMA_PP_WB_REG_NUM];
  78         __u32 plbu_array_address[4];
  79         __u32 fragment_stack_address[4];
  80 };
  81 
  82 /* frame used to setup mali450 GPU PP for each task */
  83 struct drm_lima_m450_pp_frame {
  84         __u32 frame[LIMA_PP_FRAME_REG_NUM];
  85         __u32 num_pp;
  86         __u32 wb[3 * LIMA_PP_WB_REG_NUM];
  87         __u32 use_dlbu;
  88         __u32 _pad;
  89         union {
  90                 __u32 plbu_array_address[8];
  91                 __u32 dlbu_regs[4];
  92         };
  93         __u32 fragment_stack_address[8];
  94 };
  95 
  96 #define LIMA_PIPE_GP  0x00
  97 #define LIMA_PIPE_PP  0x01
  98 
  99 #define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
 100 
 101 /**
 102  * submit a task to GPU
 103  *
 104  * User can always merge multi sync_file and drm_syncobj
 105  * into one drm_syncobj as in_sync[0], but we reserve
 106  * in_sync[1] for another task's out_sync to avoid the
 107  * export/import/merge pass when explicit sync.
 108  */
 109 struct drm_lima_gem_submit {
 110         __u32 ctx;         /* in, context handle task is submitted to */
 111         __u32 pipe;        /* in, which pipe to use, GP/PP */
 112         __u32 nr_bos;      /* in, array length of bos field */
 113         __u32 frame_size;  /* in, size of frame field */
 114         __u64 bos;         /* in, array of drm_lima_gem_submit_bo */
 115         __u64 frame;       /* in, GP/PP frame */
 116         __u32 flags;       /* in, submit flags */
 117         __u32 out_sync;    /* in, drm_syncobj handle used to wait task finish after submission */
 118         __u32 in_sync[2];  /* in, drm_syncobj handle used to wait before start this task */
 119 };
 120 
 121 #define LIMA_GEM_WAIT_READ   0x01
 122 #define LIMA_GEM_WAIT_WRITE  0x02
 123 
 124 /**
 125  * wait pending GPU task finish of a buffer
 126  */
 127 struct drm_lima_gem_wait {
 128         __u32 handle;      /* in, GEM buffer handle */
 129         __u32 op;          /* in, CPU want to read/write this buffer */
 130         __s64 timeout_ns;  /* in, wait timeout in absulute time */
 131 };
 132 
 133 /**
 134  * create a context
 135  */
 136 struct drm_lima_ctx_create {
 137         __u32 id;          /* out, context handle */
 138         __u32 _pad;        /* pad, must be zero */
 139 };
 140 
 141 /**
 142  * free a context
 143  */
 144 struct drm_lima_ctx_free {
 145         __u32 id;          /* in, context handle */
 146         __u32 _pad;        /* pad, must be zero */
 147 };
 148 
 149 #define DRM_LIMA_GET_PARAM   0x00
 150 #define DRM_LIMA_GEM_CREATE  0x01
 151 #define DRM_LIMA_GEM_INFO    0x02
 152 #define DRM_LIMA_GEM_SUBMIT  0x03
 153 #define DRM_LIMA_GEM_WAIT    0x04
 154 #define DRM_LIMA_CTX_CREATE  0x05
 155 #define DRM_LIMA_CTX_FREE    0x06
 156 
 157 #define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
 158 #define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
 159 #define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
 160 #define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
 161 #define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
 162 #define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
 163 #define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
 164 
 165 #if defined(__cplusplus)
 166 }
 167 #endif
 168 
 169 #endif /* __LIMA_DRM_H__ */