root/arch/powerpc/include/asm/eeh.h

INCLUDED FROM

DEFINITIONS

1. eeh_pe_passed
2. eeh_dev_to_pdn
3. eeh_dev_to_pci_dev
4. eeh_dev_to_pe
5. eeh_add_flag
6. eeh_clear_flag
7. eeh_has_flag
8. eeh_enabled
9. eeh_serialize_lock
10. eeh_serialize_unlock
11. eeh_state_active
12. eeh_enabled
13. eeh_show_enabled
14. eeh_dev_init
15. eeh_dev_phb_init_dynamic
16. eeh_check_failure
17. eeh_addr_cache_init
18. eeh_add_device_early
19. eeh_add_device_tree_early
20. eeh_add_device_late
21. eeh_add_device_tree_late
22. eeh_add_sysfs_files
23. eeh_remove_device
24. eeh_readb
25. eeh_readw
26. eeh_readl
27. eeh_readq
28. eeh_readw_be
29. eeh_readl_be
30. eeh_readq_be
31. eeh_memcpy_fromio
32. eeh_readsb
33. eeh_readsw
34. eeh_readsl

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   4  * Copyright 2001-2012 IBM Corporation.
   5  */
   6 
   7 #ifndef _POWERPC_EEH_H
   8 #define _POWERPC_EEH_H
   9 #ifdef __KERNEL__
  10 
  11 #include <linux/init.h>
  12 #include <linux/list.h>
  13 #include <linux/string.h>
  14 #include <linux/time.h>
  15 #include <linux/atomic.h>
  16 
  17 #include <uapi/asm/eeh.h>
  18 
  19 struct pci_dev;
  20 struct pci_bus;
  21 struct pci_dn;
  22 
  23 #ifdef CONFIG_EEH
  24 
  25 /* EEH subsystem flags */
  26 #define EEH_ENABLED             0x01    /* EEH enabled                       */
  27 #define EEH_FORCE_DISABLED      0x02    /* EEH disabled                      */
  28 #define EEH_PROBE_MODE_DEV      0x04    /* From PCI device                   */
  29 #define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree                  */
  30 #define EEH_VALID_PE_ZERO       0x10    /* PE#0 is valid                     */
  31 #define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log                 */
  32 #define EEH_EARLY_DUMP_LOG      0x40    /* Dump log immediately              */
  33 
  34 /*
  35  * Delay for PE reset, all in ms
  36  *
  37  * PCI specification has reset hold time of 100 milliseconds.
  38  * We have 250 milliseconds here. The PCI bus settlement time
  39  * is specified as 1.5 seconds and we have 1.8 seconds.
  40  */
  41 #define EEH_PE_RST_HOLD_TIME            250
  42 #define EEH_PE_RST_SETTLE_TIME          1800
  43 
  44 /*
  45  * The struct is used to trace PE related EEH functionality.
  46  * In theory, there will have one instance of the struct to
  47  * be created against particular PE. In nature, PEs correlate
  48  * to each other. the struct has to reflect that hierarchy in
  49  * order to easily pick up those affected PEs when one particular
  50  * PE has EEH errors.
  51  *
  52  * Also, one particular PE might be composed of PCI device, PCI
  53  * bus and its subordinate components. The struct also need ship
  54  * the information. Further more, one particular PE is only meaingful
  55  * in the corresponding PHB. Therefore, the root PEs should be created
  56  * against existing PHBs in on-to-one fashion.
  57  */
  58 #define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  59 #define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  60 #define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  61 #define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  62 #define EEH_PE_VF       (1 << 4)        /* VF PE     */
  63 
  64 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  65 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  66 #define EEH_PE_CFG_BLOCKED      (1 << 2)        /* Block config access  */
  67 #define EEH_PE_RESET            (1 << 3)        /* PE reset in progress */
  68 
  69 #define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  70 #define EEH_PE_CFG_RESTRICTED   (1 << 9)        /* Block config on error */
  71 #define EEH_PE_REMOVED          (1 << 10)       /* Removed permanently  */
  72 #define EEH_PE_PRI_BUS          (1 << 11)       /* Cached primary bus   */
  73 
  74 struct eeh_pe {
  75         int type;                       /* PE type: PHB/Bus/Device      */
  76         int state;                      /* PE EEH dependent mode        */
  77         int config_addr;                /* Traditional PCI address      */
  78         int addr;                       /* PE configuration address     */
  79         struct pci_controller *phb;     /* Associated PHB               */
  80         struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  81         int check_count;                /* Times of ignored error       */
  82         int freeze_count;               /* Times of froze up            */
  83         time64_t tstamp;                /* Time on first-time freeze    */
  84         int false_positives;            /* Times of reported #ff's      */
  85         atomic_t pass_dev_cnt;          /* Count of passed through devs */
  86         struct eeh_pe *parent;          /* Parent PE                    */
  87         void *data;                     /* PE auxillary data            */
  88         struct list_head child_list;    /* List of PEs below this PE    */
  89         struct list_head child;         /* Memb. child_list/eeh_phb_pe  */
  90         struct list_head edevs;         /* List of eeh_dev in this PE   */
  91 
  92 #ifdef CONFIG_STACKTRACE
  93         /*
  94          * Saved stack trace. When we find a PE freeze in eeh_dev_check_failure
  95          * the stack trace is saved here so we can print it in the recovery
  96          * thread if it turns out to due to a real problem rather than
  97          * a hot-remove.
  98          *
  99          * A max of 64 entries might be overkill, but it also might not be.
 100          */
 101         unsigned long stack_trace[64];
 102         int trace_entries;
 103 #endif /* CONFIG_STACKTRACE */
 104 };
 105 
 106 #define eeh_pe_for_each_dev(pe, edev, tmp) \
 107                 list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
 108 
 109 #define eeh_for_each_pe(root, pe) \
 110         for (pe = root; pe; pe = eeh_pe_next(pe, root))
 111 
 112 static inline bool eeh_pe_passed(struct eeh_pe *pe)
 113 {
 114         return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
 115 }
 116 
 117 /*
 118  * The struct is used to trace EEH state for the associated
 119  * PCI device node or PCI device. In future, it might
 120  * represent PE as well so that the EEH device to form
 121  * another tree except the currently existing tree of PCI
 122  * buses and PCI devices
 123  */
 124 #define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
 125 #define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
 126 #define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
 127 #define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 128 #define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 129 
 130 #define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 131 #define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 132 #define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
 133 
 134 struct eeh_dev {
 135         int mode;                       /* EEH mode                     */
 136         int class_code;                 /* Class code of the device     */
 137         int bdfn;                       /* bdfn of device (for cfg ops) */
 138         struct pci_controller *controller;
 139         int pe_config_addr;             /* PE config address            */
 140         u32 config_space[16];           /* Saved PCI config space       */
 141         int pcix_cap;                   /* Saved PCIx capability        */
 142         int pcie_cap;                   /* Saved PCIe capability        */
 143         int aer_cap;                    /* Saved AER capability         */
 144         int af_cap;                     /* Saved AF capability          */
 145         struct eeh_pe *pe;              /* Associated PE                */
 146         struct list_head entry;         /* Membership in eeh_pe.edevs   */
 147         struct list_head rmv_entry;     /* Membership in rmv_list       */
 148         struct pci_dn *pdn;             /* Associated PCI device node   */
 149         struct pci_dev *pdev;           /* Associated PCI device        */
 150         bool in_error;                  /* Error flag for edev          */
 151         struct pci_dev *physfn;         /* Associated SRIOV PF          */
 152 };
 153 
 154 /* "fmt" must be a simple literal string */
 155 #define EEH_EDEV_PRINT(level, edev, fmt, ...) \
 156         pr_##level("PCI %04x:%02x:%02x.%x#%04x: EEH: " fmt, \
 157         (edev)->controller->global_number, PCI_BUSNO((edev)->bdfn), \
 158         PCI_SLOT((edev)->bdfn), PCI_FUNC((edev)->bdfn), \
 159         ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)
 160 #define eeh_edev_dbg(edev, fmt, ...) EEH_EDEV_PRINT(debug, (edev), fmt, ##__VA_ARGS__)
 161 #define eeh_edev_info(edev, fmt, ...) EEH_EDEV_PRINT(info, (edev), fmt, ##__VA_ARGS__)
 162 #define eeh_edev_warn(edev, fmt, ...) EEH_EDEV_PRINT(warn, (edev), fmt, ##__VA_ARGS__)
 163 #define eeh_edev_err(edev, fmt, ...) EEH_EDEV_PRINT(err, (edev), fmt, ##__VA_ARGS__)
 164 
 165 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
 166 {
 167         return edev ? edev->pdn : NULL;
 168 }
 169 
 170 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 171 {
 172         return edev ? edev->pdev : NULL;
 173 }
 174 
 175 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
 176 {
 177         return edev ? edev->pe : NULL;
 178 }
 179 
 180 /* Return values from eeh_ops::next_error */
 181 enum {
 182         EEH_NEXT_ERR_NONE = 0,
 183         EEH_NEXT_ERR_INF,
 184         EEH_NEXT_ERR_FROZEN_PE,
 185         EEH_NEXT_ERR_FENCED_PHB,
 186         EEH_NEXT_ERR_DEAD_PHB,
 187         EEH_NEXT_ERR_DEAD_IOC
 188 };
 189 
 190 /*
 191  * The struct is used to trace the registered EEH operation
 192  * callback functions. Actually, those operation callback
 193  * functions are heavily platform dependent. That means the
 194  * platform should register its own EEH operation callback
 195  * functions before any EEH further operations.
 196  */
 197 #define EEH_OPT_DISABLE         0       /* EEH disable  */
 198 #define EEH_OPT_ENABLE          1       /* EEH enable   */
 199 #define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 200 #define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 201 #define EEH_OPT_FREEZE_PE       4       /* Freeze PE    */
 202 #define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 203 #define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 204 #define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 205 #define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 206 #define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 207 #define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 208 #define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 209 #define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 210 #define EEH_RESET_HOT           1       /* Hot reset                    */
 211 #define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 212 #define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 213 #define EEH_LOG_PERM            2       /* EEH permanent error log      */
 214 
 215 struct eeh_ops {
 216         char *name;
 217         int (*init)(void);
 218         void* (*probe)(struct pci_dn *pdn, void *data);
 219         int (*set_option)(struct eeh_pe *pe, int option);
 220         int (*get_pe_addr)(struct eeh_pe *pe);
 221         int (*get_state)(struct eeh_pe *pe, int *delay);
 222         int (*reset)(struct eeh_pe *pe, int option);
 223         int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 224         int (*configure_bridge)(struct eeh_pe *pe);
 225         int (*err_inject)(struct eeh_pe *pe, int type, int func,
 226                           unsigned long addr, unsigned long mask);
 227         int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
 228         int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
 229         int (*next_error)(struct eeh_pe **pe);
 230         int (*restore_config)(struct pci_dn *pdn);
 231         int (*notify_resume)(struct pci_dn *pdn);
 232 };
 233 
 234 extern int eeh_subsystem_flags;
 235 extern u32 eeh_max_freezes;
 236 extern bool eeh_debugfs_no_recover;
 237 extern struct eeh_ops *eeh_ops;
 238 extern raw_spinlock_t confirm_error_lock;
 239 
 240 static inline void eeh_add_flag(int flag)
 241 {
 242         eeh_subsystem_flags |= flag;
 243 }
 244 
 245 static inline void eeh_clear_flag(int flag)
 246 {
 247         eeh_subsystem_flags &= ~flag;
 248 }
 249 
 250 static inline bool eeh_has_flag(int flag)
 251 {
 252         return !!(eeh_subsystem_flags & flag);
 253 }
 254 
 255 static inline bool eeh_enabled(void)
 256 {
 257         return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED);
 258 }
 259 
 260 static inline void eeh_serialize_lock(unsigned long *flags)
 261 {
 262         raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 263 }
 264 
 265 static inline void eeh_serialize_unlock(unsigned long flags)
 266 {
 267         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 268 }
 269 
 270 static inline bool eeh_state_active(int state)
 271 {
 272         return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
 273         == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
 274 }
 275 
 276 typedef void (*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
 277 typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
 278 void eeh_set_pe_aux_size(int size);
 279 int eeh_phb_pe_create(struct pci_controller *phb);
 280 int eeh_wait_state(struct eeh_pe *pe, int max_wait);
 281 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 282 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
 283 struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
 284                           int pe_no, int config_addr);
 285 int eeh_add_to_parent_pe(struct eeh_dev *edev);
 286 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 287 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 288 void *eeh_pe_traverse(struct eeh_pe *root,
 289                       eeh_pe_traverse_func fn, void *flag);
 290 void eeh_pe_dev_traverse(struct eeh_pe *root,
 291                          eeh_edev_traverse_func fn, void *flag);
 292 void eeh_pe_restore_bars(struct eeh_pe *pe);
 293 const char *eeh_pe_loc_get(struct eeh_pe *pe);
 294 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 295 
 296 struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
 297 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 298 void eeh_show_enabled(void);
 299 int __init eeh_ops_register(struct eeh_ops *ops);
 300 int __exit eeh_ops_unregister(const char *name);
 301 int eeh_check_failure(const volatile void __iomem *token);
 302 int eeh_dev_check_failure(struct eeh_dev *edev);
 303 void eeh_addr_cache_init(void);
 304 void eeh_add_device_early(struct pci_dn *);
 305 void eeh_add_device_tree_early(struct pci_dn *);
 306 void eeh_add_device_late(struct pci_dev *);
 307 void eeh_add_device_tree_late(struct pci_bus *);
 308 void eeh_add_sysfs_files(struct pci_bus *);
 309 void eeh_remove_device(struct pci_dev *);
 310 int eeh_unfreeze_pe(struct eeh_pe *pe);
 311 int eeh_pe_reset_and_recover(struct eeh_pe *pe);
 312 int eeh_dev_open(struct pci_dev *pdev);
 313 void eeh_dev_release(struct pci_dev *pdev);
 314 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
 315 int eeh_pe_set_option(struct eeh_pe *pe, int option);
 316 int eeh_pe_get_state(struct eeh_pe *pe);
 317 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);
 318 int eeh_pe_configure(struct eeh_pe *pe);
 319 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
 320                       unsigned long addr, unsigned long mask);
 321 int eeh_restore_vf_config(struct pci_dn *pdn);
 322 
 323 /**
 324  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 325  *
 326  * If this macro yields TRUE, the caller relays to eeh_check_failure()
 327  * which does further tests out of line.
 328  */
 329 #define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
 330 
 331 /*
 332  * Reads from a device which has been isolated by EEH will return
 333  * all 1s.  This macro gives an all-1s value of the given size (in
 334  * bytes: 1, 2, or 4) for comparing with the result of a read.
 335  */
 336 #define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 337 
 338 #else /* !CONFIG_EEH */
 339 
 340 static inline bool eeh_enabled(void)
 341 {
 342         return false;
 343 }
 344 
 345 static inline void eeh_show_enabled(void) { }
 346 
 347 static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
 348 {
 349         return NULL;
 350 }
 351 
 352 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 353 
 354 static inline int eeh_check_failure(const volatile void __iomem *token)
 355 {
 356         return 0;
 357 }
 358 
 359 #define eeh_dev_check_failure(x) (0)
 360 
 361 static inline void eeh_addr_cache_init(void) { }
 362 
 363 static inline void eeh_add_device_early(struct pci_dn *pdn) { }
 364 
 365 static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
 366 
 367 static inline void eeh_add_device_late(struct pci_dev *dev) { }
 368 
 369 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 370 
 371 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 372 
 373 static inline void eeh_remove_device(struct pci_dev *dev) { }
 374 
 375 #define EEH_POSSIBLE_ERROR(val, type) (0)
 376 #define EEH_IO_ERROR_VALUE(size) (-1UL)
 377 #endif /* CONFIG_EEH */
 378 
 379 #ifdef CONFIG_PPC64
 380 /*
 381  * MMIO read/write operations with EEH support.
 382  */
 383 static inline u8 eeh_readb(const volatile void __iomem *addr)
 384 {
 385         u8 val = in_8(addr);
 386         if (EEH_POSSIBLE_ERROR(val, u8))
 387                 eeh_check_failure(addr);
 388         return val;
 389 }
 390 
 391 static inline u16 eeh_readw(const volatile void __iomem *addr)
 392 {
 393         u16 val = in_le16(addr);
 394         if (EEH_POSSIBLE_ERROR(val, u16))
 395                 eeh_check_failure(addr);
 396         return val;
 397 }
 398 
 399 static inline u32 eeh_readl(const volatile void __iomem *addr)
 400 {
 401         u32 val = in_le32(addr);
 402         if (EEH_POSSIBLE_ERROR(val, u32))
 403                 eeh_check_failure(addr);
 404         return val;
 405 }
 406 
 407 static inline u64 eeh_readq(const volatile void __iomem *addr)
 408 {
 409         u64 val = in_le64(addr);
 410         if (EEH_POSSIBLE_ERROR(val, u64))
 411                 eeh_check_failure(addr);
 412         return val;
 413 }
 414 
 415 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 416 {
 417         u16 val = in_be16(addr);
 418         if (EEH_POSSIBLE_ERROR(val, u16))
 419                 eeh_check_failure(addr);
 420         return val;
 421 }
 422 
 423 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 424 {
 425         u32 val = in_be32(addr);
 426         if (EEH_POSSIBLE_ERROR(val, u32))
 427                 eeh_check_failure(addr);
 428         return val;
 429 }
 430 
 431 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 432 {
 433         u64 val = in_be64(addr);
 434         if (EEH_POSSIBLE_ERROR(val, u64))
 435                 eeh_check_failure(addr);
 436         return val;
 437 }
 438 
 439 static inline void eeh_memcpy_fromio(void *dest, const
 440                                      volatile void __iomem *src,
 441                                      unsigned long n)
 442 {
 443         _memcpy_fromio(dest, src, n);
 444 
 445         /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 446          * were copied. Check all four bytes.
 447          */
 448         if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 449                 eeh_check_failure(src);
 450 }
 451 
 452 /* in-string eeh macros */
 453 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 454                               int ns)
 455 {
 456         _insb(addr, buf, ns);
 457         if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 458                 eeh_check_failure(addr);
 459 }
 460 
 461 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 462                               int ns)
 463 {
 464         _insw(addr, buf, ns);
 465         if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 466                 eeh_check_failure(addr);
 467 }
 468 
 469 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 470                               int nl)
 471 {
 472         _insl(addr, buf, nl);
 473         if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 474                 eeh_check_failure(addr);
 475 }
 476 
 477 
 478 void eeh_cache_debugfs_init(void);
 479 
 480 #endif /* CONFIG_PPC64 */
 481 #endif /* __KERNEL__ */
 482 #endif /* _POWERPC_EEH_H */