root/arch/powerpc/include/asm/io.h

INCLUDED FROM

DEFINITIONS

1. in_le64
2. out_le64
3. in_be64
4. out_be64
5. __raw_readb
6. __raw_readw
7. __raw_readl
8. __raw_writeb
9. __raw_writew
10. __raw_writel
11. __raw_readq
12. __raw_writeq
13. __raw_writeq_be
14. __raw_rm_writeb
15. __raw_rm_writew
16. __raw_rm_writel
17. __raw_rm_writeq
18. __raw_rm_writeq_be
19. __raw_rm_readb
20. __raw_rm_readw
21. __raw_rm_readl
22. __raw_rm_readq
23. iosync
24. virt_to_phys
25. phys_to_virt
26. page_to_phys
27. virt_to_bus
28. bus_to_virt

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 #ifndef _ASM_POWERPC_IO_H
   3 #define _ASM_POWERPC_IO_H
   4 #ifdef __KERNEL__
   5 
   6 #define ARCH_HAS_IOREMAP_WC
   7 #ifdef CONFIG_PPC32
   8 #define ARCH_HAS_IOREMAP_WT
   9 #endif
  10 
  11 /*
  12  */
  13 
  14 /* Check of existence of legacy devices */
  15 extern int check_legacy_ioport(unsigned long base_port);
  16 #define I8042_DATA_REG  0x60
  17 #define FDC_BASE        0x3f0
  18 
  19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
  20 extern struct pci_dev *isa_bridge_pcidev;
  21 /*
  22  * has legacy ISA devices ?
  23  */
  24 #define arch_has_dev_port()     (isa_bridge_pcidev != NULL || isa_io_special)
  25 #endif
  26 
  27 #include <linux/device.h>
  28 #include <linux/compiler.h>
  29 #include <linux/mm.h>
  30 #include <asm/page.h>
  31 #include <asm/byteorder.h>
  32 #include <asm/synch.h>
  33 #include <asm/delay.h>
  34 #include <asm/mmiowb.h>
  35 #include <asm/mmu.h>
  36 #include <asm/ppc_asm.h>
  37 #include <asm/pgtable.h>
  38 
  39 #define SIO_CONFIG_RA   0x398
  40 #define SIO_CONFIG_RD   0x399
  41 
  42 #define SLOW_DOWN_IO
  43 
  44 /* 32 bits uses slightly different variables for the various IO
  45  * bases. Most of this file only uses _IO_BASE though which we
  46  * define properly based on the platform
  47  */
  48 #ifndef CONFIG_PCI
  49 #define _IO_BASE        0
  50 #define _ISA_MEM_BASE   0
  51 #define PCI_DRAM_OFFSET 0
  52 #elif defined(CONFIG_PPC32)
  53 #define _IO_BASE        isa_io_base
  54 #define _ISA_MEM_BASE   isa_mem_base
  55 #define PCI_DRAM_OFFSET pci_dram_offset
  56 #else
  57 #define _IO_BASE        pci_io_base
  58 #define _ISA_MEM_BASE   isa_mem_base
  59 #define PCI_DRAM_OFFSET 0
  60 #endif
  61 
  62 extern unsigned long isa_io_base;
  63 extern unsigned long pci_io_base;
  64 extern unsigned long pci_dram_offset;
  65 
  66 extern resource_size_t isa_mem_base;
  67 
  68 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
  69  * is not set or addresses cannot be translated to MMIO. This is typically
  70  * set when the platform supports "special" PIO accesses via a non memory
  71  * mapped mechanism, and allows things like the early udbg UART code to
  72  * function.
  73  */
  74 extern bool isa_io_special;
  75 
  76 #ifdef CONFIG_PPC32
  77 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
  78 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
  79 #endif
  80 #endif
  81 
  82 /*
  83  *
  84  * Low level MMIO accessors
  85  *
  86  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  87  * specific and thus shouldn't be used in generic code. The accessors
  88  * provided here are:
  89  *
  90  *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  91  *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  92  *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  93  *
  94  * Those operate directly on a kernel virtual address. Note that the prototype
  95  * for the out_* accessors has the arguments in opposite order from the usual
  96  * linux PCI accessors. Unlike those, they take the address first and the value
  97  * next.
  98  *
  99  * Note: I might drop the _ns suffix on the stream operations soon as it is
 100  * simply normal for stream operations to not swap in the first place.
 101  *
 102  */
 103 
 104 #define DEF_MMIO_IN_X(name, size, insn)                         \
 105 static inline u##size name(const volatile u##size __iomem *addr)        \
 106 {                                                                       \
 107         u##size ret;                                                    \
 108         __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"     \
 109                 : "=r" (ret) : "Z" (*addr) : "memory");                 \
 110         return ret;                                                     \
 111 }
 112 
 113 #define DEF_MMIO_OUT_X(name, size, insn)                                \
 114 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 115 {                                                                       \
 116         __asm__ __volatile__("sync;"#insn" %1,%y0"                      \
 117                 : "=Z" (*addr) : "r" (val) : "memory");                 \
 118         mmiowb_set_pending();                                           \
 119 }
 120 
 121 #define DEF_MMIO_IN_D(name, size, insn)                         \
 122 static inline u##size name(const volatile u##size __iomem *addr)        \
 123 {                                                                       \
 124         u##size ret;                                                    \
 125         __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
 126                 : "=r" (ret) : "m" (*addr) : "memory");                 \
 127         return ret;                                                     \
 128 }
 129 
 130 #define DEF_MMIO_OUT_D(name, size, insn)                                \
 131 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 132 {                                                                       \
 133         __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"                 \
 134                 : "=m" (*addr) : "r" (val) : "memory");                 \
 135         mmiowb_set_pending();                                           \
 136 }
 137 
 138 DEF_MMIO_IN_D(in_8,     8, lbz);
 139 DEF_MMIO_OUT_D(out_8,   8, stb);
 140 
 141 #ifdef __BIG_ENDIAN__
 142 DEF_MMIO_IN_D(in_be16, 16, lhz);
 143 DEF_MMIO_IN_D(in_be32, 32, lwz);
 144 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
 145 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
 146 
 147 DEF_MMIO_OUT_D(out_be16, 16, sth);
 148 DEF_MMIO_OUT_D(out_be32, 32, stw);
 149 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
 150 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
 151 #else
 152 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
 153 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
 154 DEF_MMIO_IN_D(in_le16, 16, lhz);
 155 DEF_MMIO_IN_D(in_le32, 32, lwz);
 156 
 157 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
 158 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
 159 DEF_MMIO_OUT_D(out_le16, 16, sth);
 160 DEF_MMIO_OUT_D(out_le32, 32, stw);
 161 
 162 #endif /* __BIG_ENDIAN */
 163 
 164 #ifdef __powerpc64__
 165 
 166 #ifdef __BIG_ENDIAN__
 167 DEF_MMIO_OUT_D(out_be64, 64, std);
 168 DEF_MMIO_IN_D(in_be64, 64, ld);
 169 
 170 /* There is no asm instructions for 64 bits reverse loads and stores */
 171 static inline u64 in_le64(const volatile u64 __iomem *addr)
 172 {
 173         return swab64(in_be64(addr));
 174 }
 175 
 176 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
 177 {
 178         out_be64(addr, swab64(val));
 179 }
 180 #else
 181 DEF_MMIO_OUT_D(out_le64, 64, std);
 182 DEF_MMIO_IN_D(in_le64, 64, ld);
 183 
 184 /* There is no asm instructions for 64 bits reverse loads and stores */
 185 static inline u64 in_be64(const volatile u64 __iomem *addr)
 186 {
 187         return swab64(in_le64(addr));
 188 }
 189 
 190 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
 191 {
 192         out_le64(addr, swab64(val));
 193 }
 194 
 195 #endif
 196 #endif /* __powerpc64__ */
 197 
 198 /*
 199  * Low level IO stream instructions are defined out of line for now
 200  */
 201 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
 202 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
 203 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
 204 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
 205 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
 206 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 207 
 208 /* The _ns naming is historical and will be removed. For now, just #define
 209  * the non _ns equivalent names
 210  */
 211 #define _insw   _insw_ns
 212 #define _insl   _insl_ns
 213 #define _outsw  _outsw_ns
 214 #define _outsl  _outsl_ns
 215 
 216 
 217 /*
 218  * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
 219  */
 220 
 221 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
 222 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
 223                            unsigned long n);
 224 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
 225                          unsigned long n);
 226 
 227 /*
 228  *
 229  * PCI and standard ISA accessors
 230  *
 231  * Those are globally defined linux accessors for devices on PCI or ISA
 232  * busses. They follow the Linux defined semantics. The current implementation
 233  * for PowerPC is as close as possible to the x86 version of these, and thus
 234  * provides fairly heavy weight barriers for the non-raw versions
 235  *
 236  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
 237  * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
 238  * own implementation of some or all of the accessors.
 239  */
 240 
 241 /*
 242  * Include the EEH definitions when EEH is enabled only so they don't get
 243  * in the way when building for 32 bits
 244  */
 245 #ifdef CONFIG_EEH
 246 #include <asm/eeh.h>
 247 #endif
 248 
 249 /* Shortcut to the MMIO argument pointer */
 250 #define PCI_IO_ADDR     volatile void __iomem *
 251 
 252 /* Indirect IO address tokens:
 253  *
 254  * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
 255  * on all MMIOs. (Note that this is all 64 bits only for now)
 256  *
 257  * To help platforms who may need to differentiate MMIO addresses in
 258  * their hooks, a bitfield is reserved for use by the platform near the
 259  * top of MMIO addresses (not PIO, those have to cope the hard way).
 260  *
 261  * The highest address in the kernel virtual space are:
 262  *
 263  *  d0003fffffffffff    # with Hash MMU
 264  *  c00fffffffffffff    # with Radix MMU
 265  *
 266  * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
 267  * that can be used for the field.
 268  *
 269  * The direct IO mapping operations will then mask off those bits
 270  * before doing the actual access, though that only happen when
 271  * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
 272  * mechanism
 273  *
 274  * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
 275  * all PIO functions call through a hook.
 276  */
 277 
 278 #ifdef CONFIG_PPC_INDIRECT_MMIO
 279 #define PCI_IO_IND_TOKEN_SHIFT  52
 280 #define PCI_IO_IND_TOKEN_MASK   (0xfful << PCI_IO_IND_TOKEN_SHIFT)
 281 #define PCI_FIX_ADDR(addr)                                              \
 282         ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
 283 #define PCI_GET_ADDR_TOKEN(addr)                                        \
 284         (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
 285                 PCI_IO_IND_TOKEN_SHIFT)
 286 #define PCI_SET_ADDR_TOKEN(addr, token)                                 \
 287 do {                                                                    \
 288         unsigned long __a = (unsigned long)(addr);                      \
 289         __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
 290         __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
 291         (addr) = (void __iomem *)__a;                                   \
 292 } while(0)
 293 #else
 294 #define PCI_FIX_ADDR(addr) (addr)
 295 #endif
 296 
 297 
 298 /*
 299  * Non ordered and non-swapping "raw" accessors
 300  */
 301 
 302 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 303 {
 304         return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
 305 }
 306 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 307 {
 308         return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
 309 }
 310 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 311 {
 312         return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
 313 }
 314 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 315 {
 316         *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
 317 }
 318 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 319 {
 320         *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
 321 }
 322 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 323 {
 324         *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
 325 }
 326 
 327 #ifdef __powerpc64__
 328 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
 329 {
 330         return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
 331 }
 332 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 333 {
 334         *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
 335 }
 336 
 337 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
 338 {
 339         __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
 340 }
 341 
 342 /*
 343  * Real mode versions of the above. Those instructions are only supposed
 344  * to be used in hypervisor real mode as per the architecture spec.
 345  */
 346 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
 347 {
 348         __asm__ __volatile__("stbcix %0,0,%1"
 349                 : : "r" (val), "r" (paddr) : "memory");
 350 }
 351 
 352 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
 353 {
 354         __asm__ __volatile__("sthcix %0,0,%1"
 355                 : : "r" (val), "r" (paddr) : "memory");
 356 }
 357 
 358 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
 359 {
 360         __asm__ __volatile__("stwcix %0,0,%1"
 361                 : : "r" (val), "r" (paddr) : "memory");
 362 }
 363 
 364 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
 365 {
 366         __asm__ __volatile__("stdcix %0,0,%1"
 367                 : : "r" (val), "r" (paddr) : "memory");
 368 }
 369 
 370 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
 371 {
 372         __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
 373 }
 374 
 375 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
 376 {
 377         u8 ret;
 378         __asm__ __volatile__("lbzcix %0,0, %1"
 379                              : "=r" (ret) : "r" (paddr) : "memory");
 380         return ret;
 381 }
 382 
 383 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
 384 {
 385         u16 ret;
 386         __asm__ __volatile__("lhzcix %0,0, %1"
 387                              : "=r" (ret) : "r" (paddr) : "memory");
 388         return ret;
 389 }
 390 
 391 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
 392 {
 393         u32 ret;
 394         __asm__ __volatile__("lwzcix %0,0, %1"
 395                              : "=r" (ret) : "r" (paddr) : "memory");
 396         return ret;
 397 }
 398 
 399 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
 400 {
 401         u64 ret;
 402         __asm__ __volatile__("ldcix %0,0, %1"
 403                              : "=r" (ret) : "r" (paddr) : "memory");
 404         return ret;
 405 }
 406 #endif /* __powerpc64__ */
 407 
 408 /*
 409  *
 410  * PCI PIO and MMIO accessors.
 411  *
 412  *
 413  * On 32 bits, PIO operations have a recovery mechanism in case they trigger
 414  * machine checks (which they occasionally do when probing non existing
 415  * IO ports on some platforms, like PowerMac and 8xx).
 416  * I always found it to be of dubious reliability and I am tempted to get
 417  * rid of it one of these days. So if you think it's important to keep it,
 418  * please voice up asap. We never had it for 64 bits and I do not intend
 419  * to port it over
 420  */
 421 
 422 #ifdef CONFIG_PPC32
 423 
 424 #define __do_in_asm(name, op)                           \
 425 static inline unsigned int name(unsigned int port)      \
 426 {                                                       \
 427         unsigned int x;                                 \
 428         __asm__ __volatile__(                           \
 429                 "sync\n"                                \
 430                 "0:"    op "    %0,0,%1\n"              \
 431                 "1:     twi     0,%0,0\n"               \
 432                 "2:     isync\n"                        \
 433                 "3:     nop\n"                          \
 434                 "4:\n"                                  \
 435                 ".section .fixup,\"ax\"\n"              \
 436                 "5:     li      %0,-1\n"                \
 437                 "       b       4b\n"                   \
 438                 ".previous\n"                           \
 439                 EX_TABLE(0b, 5b)                        \
 440                 EX_TABLE(1b, 5b)                        \
 441                 EX_TABLE(2b, 5b)                        \
 442                 EX_TABLE(3b, 5b)                        \
 443                 : "=&r" (x)                             \
 444                 : "r" (port + _IO_BASE)                 \
 445                 : "memory");                            \
 446         return x;                                       \
 447 }
 448 
 449 #define __do_out_asm(name, op)                          \
 450 static inline void name(unsigned int val, unsigned int port) \
 451 {                                                       \
 452         __asm__ __volatile__(                           \
 453                 "sync\n"                                \
 454                 "0:" op " %0,0,%1\n"                    \
 455                 "1:     sync\n"                         \
 456                 "2:\n"                                  \
 457                 EX_TABLE(0b, 2b)                        \
 458                 EX_TABLE(1b, 2b)                        \
 459                 : : "r" (val), "r" (port + _IO_BASE)    \
 460                 : "memory");                            \
 461 }
 462 
 463 __do_in_asm(_rec_inb, "lbzx")
 464 __do_in_asm(_rec_inw, "lhbrx")
 465 __do_in_asm(_rec_inl, "lwbrx")
 466 __do_out_asm(_rec_outb, "stbx")
 467 __do_out_asm(_rec_outw, "sthbrx")
 468 __do_out_asm(_rec_outl, "stwbrx")
 469 
 470 #endif /* CONFIG_PPC32 */
 471 
 472 /* The "__do_*" operations below provide the actual "base" implementation
 473  * for each of the defined accessors. Some of them use the out_* functions
 474  * directly, some of them still use EEH, though we might change that in the
 475  * future. Those macros below provide the necessary argument swapping and
 476  * handling of the IO base for PIO.
 477  *
 478  * They are themselves used by the macros that define the actual accessors
 479  * and can be used by the hooks if any.
 480  *
 481  * Note that PIO operations are always defined in terms of their corresonding
 482  * MMIO operations. That allows platforms like iSeries who want to modify the
 483  * behaviour of both to only hook on the MMIO version and get both. It's also
 484  * possible to hook directly at the toplevel PIO operation if they have to
 485  * be handled differently
 486  */
 487 #define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
 488 #define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
 489 #define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
 490 #define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
 491 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
 492 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
 493 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
 494 
 495 #ifdef CONFIG_EEH
 496 #define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
 497 #define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
 498 #define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
 499 #define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
 500 #define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
 501 #define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
 502 #define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
 503 #else /* CONFIG_EEH */
 504 #define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
 505 #define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
 506 #define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
 507 #define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
 508 #define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
 509 #define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
 510 #define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
 511 #endif /* !defined(CONFIG_EEH) */
 512 
 513 #ifdef CONFIG_PPC32
 514 #define __do_outb(val, port)    _rec_outb(val, port)
 515 #define __do_outw(val, port)    _rec_outw(val, port)
 516 #define __do_outl(val, port)    _rec_outl(val, port)
 517 #define __do_inb(port)          _rec_inb(port)
 518 #define __do_inw(port)          _rec_inw(port)
 519 #define __do_inl(port)          _rec_inl(port)
 520 #else /* CONFIG_PPC32 */
 521 #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
 522 #define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
 523 #define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
 524 #define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
 525 #define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
 526 #define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
 527 #endif /* !CONFIG_PPC32 */
 528 
 529 #ifdef CONFIG_EEH
 530 #define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
 531 #define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
 532 #define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
 533 #else /* CONFIG_EEH */
 534 #define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
 535 #define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
 536 #define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
 537 #endif /* !CONFIG_EEH */
 538 #define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
 539 #define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
 540 #define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
 541 
 542 #define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 543 #define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 544 #define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 545 #define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 546 #define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 547 #define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 548 
 549 #define __do_memset_io(addr, c, n)      \
 550                                 _memset_io(PCI_FIX_ADDR(addr), c, n)
 551 #define __do_memcpy_toio(dst, src, n)   \
 552                                 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
 553 
 554 #ifdef CONFIG_EEH
 555 #define __do_memcpy_fromio(dst, src, n) \
 556                                 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
 557 #else /* CONFIG_EEH */
 558 #define __do_memcpy_fromio(dst, src, n) \
 559                                 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
 560 #endif /* !CONFIG_EEH */
 561 
 562 #ifdef CONFIG_PPC_INDIRECT_PIO
 563 #define DEF_PCI_HOOK_pio(x)     x
 564 #else
 565 #define DEF_PCI_HOOK_pio(x)     NULL
 566 #endif
 567 
 568 #ifdef CONFIG_PPC_INDIRECT_MMIO
 569 #define DEF_PCI_HOOK_mem(x)     x
 570 #else
 571 #define DEF_PCI_HOOK_mem(x)     NULL
 572 #endif
 573 
 574 /* Structure containing all the hooks */
 575 extern struct ppc_pci_io {
 576 
 577 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
 578 #define DEF_PCI_AC_NORET(name, at, al, space, aa)       void (*name) at;
 579 
 580 #include <asm/io-defs.h>
 581 
 582 #undef DEF_PCI_AC_RET
 583 #undef DEF_PCI_AC_NORET
 584 
 585 } ppc_pci_io;
 586 
 587 /* The inline wrappers */
 588 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
 589 static inline ret name at                                       \
 590 {                                                               \
 591         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)      \
 592                 return ppc_pci_io.name al;                      \
 593         return __do_##name al;                                  \
 594 }
 595 
 596 #define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
 597 static inline void name at                                      \
 598 {                                                               \
 599         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)              \
 600                 ppc_pci_io.name al;                             \
 601         else                                                    \
 602                 __do_##name al;                                 \
 603 }
 604 
 605 #include <asm/io-defs.h>
 606 
 607 #undef DEF_PCI_AC_RET
 608 #undef DEF_PCI_AC_NORET
 609 
 610 /* Some drivers check for the presence of readq & writeq with
 611  * a #ifdef, so we make them happy here.
 612  */
 613 #ifdef __powerpc64__
 614 #define readq   readq
 615 #define writeq  writeq
 616 #endif
 617 
 618 /*
 619  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 620  * access
 621  */
 622 #define xlate_dev_mem_ptr(p)    __va(p)
 623 
 624 /*
 625  * Convert a virtual cached pointer to an uncached pointer
 626  */
 627 #define xlate_dev_kmem_ptr(p)   p
 628 
 629 /*
 630  * We don't do relaxed operations yet, at least not with this semantic
 631  */
 632 #define readb_relaxed(addr)     readb(addr)
 633 #define readw_relaxed(addr)     readw(addr)
 634 #define readl_relaxed(addr)     readl(addr)
 635 #define readq_relaxed(addr)     readq(addr)
 636 #define writeb_relaxed(v, addr) writeb(v, addr)
 637 #define writew_relaxed(v, addr) writew(v, addr)
 638 #define writel_relaxed(v, addr) writel(v, addr)
 639 #define writeq_relaxed(v, addr) writeq(v, addr)
 640 
 641 #include <asm-generic/iomap.h>
 642 
 643 static inline void iosync(void)
 644 {
 645         __asm__ __volatile__ ("sync" : : : "memory");
 646 }
 647 
 648 /* Enforce in-order execution of data I/O.
 649  * No distinction between read/write on PPC; use eieio for all three.
 650  * Those are fairly week though. They don't provide a barrier between
 651  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
 652  * they only provide barriers between 2 __raw MMIO operations and
 653  * possibly break write combining.
 654  */
 655 #define iobarrier_rw() eieio()
 656 #define iobarrier_r()  eieio()
 657 #define iobarrier_w()  eieio()
 658 
 659 
 660 /*
 661  * output pause versions need a delay at least for the
 662  * w83c105 ide controller in a p610.
 663  */
 664 #define inb_p(port)             inb(port)
 665 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
 666 #define inw_p(port)             inw(port)
 667 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
 668 #define inl_p(port)             inl(port)
 669 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
 670 
 671 
 672 #define IO_SPACE_LIMIT ~(0UL)
 673 
 674 
 675 /**
 676  * ioremap     -   map bus memory into CPU space
 677  * @address:   bus address of the memory
 678  * @size:      size of the resource to map
 679  *
 680  * ioremap performs a platform specific sequence of operations to
 681  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 682  * writew/writel functions and the other mmio helpers. The returned
 683  * address is not guaranteed to be usable directly as a virtual
 684  * address.
 685  *
 686  * We provide a few variations of it:
 687  *
 688  * * ioremap is the standard one and provides non-cacheable guarded mappings
 689  *   and can be hooked by the platform via ppc_md
 690  *
 691  * * ioremap_prot allows to specify the page flags as an argument and can
 692  *   also be hooked by the platform via ppc_md.
 693  *
 694  * * ioremap_nocache is identical to ioremap
 695  *
 696  * * ioremap_wc enables write combining
 697  *
 698  * * ioremap_wt enables write through
 699  *
 700  * * ioremap_coherent maps coherent cached memory
 701  *
 702  * * iounmap undoes such a mapping and can be hooked
 703  *
 704  * * __ioremap_at (and the pending __iounmap_at) are low level functions to
 705  *   create hand-made mappings for use only by the PCI code and cannot
 706  *   currently be hooked. Must be page aligned.
 707  *
 708  * * __ioremap_caller is the same as above but takes an explicit caller
 709  *   reference rather than using __builtin_return_address(0)
 710  *
 711  */
 712 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 713 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
 714                                   unsigned long flags);
 715 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
 716 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
 717 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
 718 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 719 #define ioremap_uc(addr, size)          ioremap((addr), (size))
 720 #define ioremap_cache(addr, size) \
 721         ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
 722 
 723 extern void iounmap(volatile void __iomem *addr);
 724 
 725 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
 726                         unsigned long size, pgprot_t prot);
 727 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
 728                          pgprot_t prot, void *caller);
 729 
 730 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
 731                                       pgprot_t prot, void *caller);
 732 
 733 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
 734                                    unsigned long size, pgprot_t prot);
 735 extern void __iounmap_at(void *ea, unsigned long size);
 736 
 737 /*
 738  * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
 739  * which needs some additional definitions here. They basically allow PIO
 740  * space overall to be 1GB. This will work as long as we never try to use
 741  * iomap to map MMIO below 1GB which should be fine on ppc64
 742  */
 743 #define HAVE_ARCH_PIO_SIZE              1
 744 #define PIO_OFFSET                      0x00000000UL
 745 #define PIO_MASK                        (FULL_IO_SIZE - 1)
 746 #define PIO_RESERVED                    (FULL_IO_SIZE)
 747 
 748 #define mmio_read16be(addr)             readw_be(addr)
 749 #define mmio_read32be(addr)             readl_be(addr)
 750 #define mmio_read64be(addr)             readq_be(addr)
 751 #define mmio_write16be(val, addr)       writew_be(val, addr)
 752 #define mmio_write32be(val, addr)       writel_be(val, addr)
 753 #define mmio_write64be(val, addr)       writeq_be(val, addr)
 754 #define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
 755 #define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
 756 #define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
 757 #define mmio_outsb(addr, src, count)    writesb(addr, src, count)
 758 #define mmio_outsw(addr, src, count)    writesw(addr, src, count)
 759 #define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 760 
 761 /**
 762  *      virt_to_phys    -       map virtual addresses to physical
 763  *      @address: address to remap
 764  *
 765  *      The returned physical address is the physical (CPU) mapping for
 766  *      the memory address given. It is only valid to use this function on
 767  *      addresses directly mapped or allocated via kmalloc.
 768  *
 769  *      This function does not give bus mappings for DMA transfers. In
 770  *      almost all conceivable cases a device driver should not be using
 771  *      this function
 772  */
 773 static inline unsigned long virt_to_phys(volatile void * address)
 774 {
 775         WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
 776 
 777         return __pa((unsigned long)address);
 778 }
 779 
 780 /**
 781  *      phys_to_virt    -       map physical address to virtual
 782  *      @address: address to remap
 783  *
 784  *      The returned virtual address is a current CPU mapping for
 785  *      the memory address given. It is only valid to use this function on
 786  *      addresses that have a kernel mapping
 787  *
 788  *      This function does not handle bus mappings for DMA transfers. In
 789  *      almost all conceivable cases a device driver should not be using
 790  *      this function
 791  */
 792 static inline void * phys_to_virt(unsigned long address)
 793 {
 794         return (void *)__va(address);
 795 }
 796 
 797 /*
 798  * Change "struct page" to physical address.
 799  */
 800 static inline phys_addr_t page_to_phys(struct page *page)
 801 {
 802         unsigned long pfn = page_to_pfn(page);
 803 
 804         WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
 805 
 806         return PFN_PHYS(pfn);
 807 }
 808 
 809 /*
 810  * 32 bits still uses virt_to_bus() for it's implementation of DMA
 811  * mappings se we have to keep it defined here. We also have some old
 812  * drivers (shame shame shame) that use bus_to_virt() and haven't been
 813  * fixed yet so I need to define it here.
 814  */
 815 #ifdef CONFIG_PPC32
 816 
 817 static inline unsigned long virt_to_bus(volatile void * address)
 818 {
 819         if (address == NULL)
 820                 return 0;
 821         return __pa(address) + PCI_DRAM_OFFSET;
 822 }
 823 
 824 static inline void * bus_to_virt(unsigned long address)
 825 {
 826         if (address == 0)
 827                 return NULL;
 828         return __va(address - PCI_DRAM_OFFSET);
 829 }
 830 
 831 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 832 
 833 #endif /* CONFIG_PPC32 */
 834 
 835 /* access ports */
 836 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
 837 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
 838 
 839 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
 840 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
 841 
 842 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
 843 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
 844 
 845 /* Clear and set bits in one shot.  These macros can be used to clear and
 846  * set multiple bits in a register using a single read-modify-write.  These
 847  * macros can also be used to set a multiple-bit bit pattern using a mask,
 848  * by specifying the mask in the 'clear' parameter and the new bit pattern
 849  * in the 'set' parameter.
 850  */
 851 
 852 #define clrsetbits(type, addr, clear, set) \
 853         out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 854 
 855 #ifdef __powerpc64__
 856 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
 857 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
 858 #endif
 859 
 860 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 861 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 862 
 863 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 864 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 865 
 866 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 867 
 868 #endif /* __KERNEL__ */
 869 
 870 #endif /* _ASM_POWERPC_IO_H */