root/arch/powerpc/include/asm/nohash/32/mmu-40x.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_MMU_40X_H_
   3 #define _ASM_POWERPC_MMU_40X_H_
   4 
   5 /*
   6  * PPC40x support
   7  */
   8 
   9 #define PPC40X_TLB_SIZE 64
  10 
  11 /*
  12  * TLB entries are defined by a "high" tag portion and a "low" data
  13  * portion.  On all architectures, the data portion is 32-bits.
  14  *
  15  * TLB entries are managed entirely under software control by reading,
  16  * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
  17  * instructions.
  18  */
  19 
  20 #define TLB_LO          1
  21 #define TLB_HI          0
  22 
  23 #define TLB_DATA        TLB_LO
  24 #define TLB_TAG         TLB_HI
  25 
  26 /* Tag portion */
  27 
  28 #define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
  29 #define TLB_PAGESZ_MASK 0x00000380
  30 #define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
  31 #define   PAGESZ_1K             0
  32 #define   PAGESZ_4K             1
  33 #define   PAGESZ_16K            2
  34 #define   PAGESZ_64K            3
  35 #define   PAGESZ_256K           4
  36 #define   PAGESZ_1M             5
  37 #define   PAGESZ_4M             6
  38 #define   PAGESZ_16M            7
  39 #define TLB_VALID       0x00000040      /* Entry is valid */
  40 
  41 /* Data portion */
  42 
  43 #define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
  44 #define TLB_PERM_MASK   0x00000300
  45 #define TLB_EX          0x00000200      /* Instruction execution allowed */
  46 #define TLB_WR          0x00000100      /* Writes permitted */
  47 #define TLB_ZSEL_MASK   0x000000F0
  48 #define TLB_ZSEL(x)     (((x) & 0xF) << 4)
  49 #define TLB_ATTR_MASK   0x0000000F
  50 #define TLB_W           0x00000008      /* Caching is write-through */
  51 #define TLB_I           0x00000004      /* Caching is inhibited */
  52 #define TLB_M           0x00000002      /* Memory is coherent */
  53 #define TLB_G           0x00000001      /* Memory is guarded from prefetch */
  54 
  55 #ifndef __ASSEMBLY__
  56 
  57 typedef struct {
  58         unsigned int    id;
  59         unsigned int    active;
  60         unsigned long   vdso_base;
  61 } mm_context_t;
  62 
  63 #endif /* !__ASSEMBLY__ */
  64 
  65 #define mmu_virtual_psize       MMU_PAGE_4K
  66 #define mmu_linear_psize        MMU_PAGE_256M
  67 
  68 #endif /* _ASM_POWERPC_MMU_40X_H_ */