arch/powerpc/mm/nohash/44x.c

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This source file includes following definitions.
ppc44x_update_tlb_hwater
ppc44x_pin_tlb
ppc47x_find_free_bolted
ppc47x_update_boltmap
ppc47x_pin_tlb
MMU_init_hw
mmu_mapin_ram
setup_initial_memory_limit
mmu_init_secondary
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Modifications by Matt Porter (mporter@mvista.com) to support
   4  * PPC44x Book E processors.
   5  *
   6  * This file contains the routines for initializing the MMU
   7  * on the 4xx series of chips.
   8  *  -- paulus
   9  *
  10  *  Derived from arch/ppc/mm/init.c:
  11  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  12  *
  13  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  14  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  15  *    Copyright (C) 1996 Paul Mackerras
  16  *
  17  *  Derived from "arch/i386/mm/init.c"
  18  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  19  */
  20 
  21 #include <linux/init.h>
  22 #include <linux/memblock.h>
  23 
  24 #include <asm/mmu.h>
  25 #include <asm/page.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/code-patching.h>
  28 
  29 #include <mm/mmu_decl.h>
  30 
  31 /* Used by the 44x TLB replacement exception handler.
  32  * Just needed it declared someplace.
  33  */
  34 unsigned int tlb_44x_index; /* = 0 */
  35 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
  36 int icache_44x_need_flush;
  37 
  38 unsigned long tlb_47x_boltmap[1024/8];
  39 
  40 static void ppc44x_update_tlb_hwater(void)
  41 {
  42         /* The TLB miss handlers hard codes the watermark in a cmpli
  43          * instruction to improve performances rather than loading it
  44          * from the global variable. Thus, we patch the instructions
  45          * in the 2 TLB miss handlers when updating the value
  46          */
  47         modify_instruction_site(&patch__tlb_44x_hwater_D, 0xffff, tlb_44x_hwater);
  48         modify_instruction_site(&patch__tlb_44x_hwater_I, 0xffff, tlb_44x_hwater);
  49 }
  50 
  51 /*
  52  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
  53  */
  54 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
  55 {
  56         unsigned int entry = tlb_44x_hwater--;
  57 
  58         ppc44x_update_tlb_hwater();
  59 
  60         mtspr(SPRN_MMUCR, 0);
  61 
  62         __asm__ __volatile__(
  63                 "tlbwe  %2,%3,%4\n"
  64                 "tlbwe  %1,%3,%5\n"
  65                 "tlbwe  %0,%3,%6\n"
  66         :
  67         : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
  68           "r" (phys),
  69           "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
  70           "r" (entry),
  71           "i" (PPC44x_TLB_PAGEID),
  72           "i" (PPC44x_TLB_XLAT),
  73           "i" (PPC44x_TLB_ATTRIB));
  74 }
  75 
  76 static int __init ppc47x_find_free_bolted(void)
  77 {
  78         unsigned int mmube0 = mfspr(SPRN_MMUBE0);
  79         unsigned int mmube1 = mfspr(SPRN_MMUBE1);
  80 
  81         if (!(mmube0 & MMUBE0_VBE0))
  82                 return 0;
  83         if (!(mmube0 & MMUBE0_VBE1))
  84                 return 1;
  85         if (!(mmube0 & MMUBE0_VBE2))
  86                 return 2;
  87         if (!(mmube1 & MMUBE1_VBE3))
  88                 return 3;
  89         if (!(mmube1 & MMUBE1_VBE4))
  90                 return 4;
  91         if (!(mmube1 & MMUBE1_VBE5))
  92                 return 5;
  93         return -1;
  94 }
  95 
  96 static void __init ppc47x_update_boltmap(void)
  97 {
  98         unsigned int mmube0 = mfspr(SPRN_MMUBE0);
  99         unsigned int mmube1 = mfspr(SPRN_MMUBE1);
 100 
 101         if (mmube0 & MMUBE0_VBE0)
 102                 __set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
 103                           tlb_47x_boltmap);
 104         if (mmube0 & MMUBE0_VBE1)
 105                 __set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
 106                           tlb_47x_boltmap);
 107         if (mmube0 & MMUBE0_VBE2)
 108                 __set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
 109                           tlb_47x_boltmap);
 110         if (mmube1 & MMUBE1_VBE3)
 111                 __set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
 112                           tlb_47x_boltmap);
 113         if (mmube1 & MMUBE1_VBE4)
 114                 __set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
 115                           tlb_47x_boltmap);
 116         if (mmube1 & MMUBE1_VBE5)
 117                 __set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
 118                           tlb_47x_boltmap);
 119 }
 120 
 121 /*
 122  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
 123  */
 124 static void ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
 125 {
 126         unsigned int rA;
 127         int bolted;
 128 
 129         /* Base rA is HW way select, way 0, bolted bit set */
 130         rA = 0x88000000;
 131 
 132         /* Look for a bolted entry slot */
 133         bolted = ppc47x_find_free_bolted();
 134         BUG_ON(bolted < 0);
 135 
 136         /* Insert bolted slot number */
 137         rA |= bolted << 24;
 138 
 139         pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
 140                  virt, phys, bolted);
 141 
 142         mtspr(SPRN_MMUCR, 0);
 143 
 144         __asm__ __volatile__(
 145                 "tlbwe  %2,%3,0\n"
 146                 "tlbwe  %1,%3,1\n"
 147                 "tlbwe  %0,%3,2\n"
 148                 :
 149                 : "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
 150                        PPC47x_TLB2_SX
 151 #ifdef CONFIG_SMP
 152                        | PPC47x_TLB2_M
 153 #endif
 154                        ),
 155                   "r" (phys),
 156                   "r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
 157                   "r" (rA));
 158 }
 159 
 160 void __init MMU_init_hw(void)
 161 {
 162         /* This is not useful on 47x but won't hurt either */
 163         ppc44x_update_tlb_hwater();
 164 
 165         flush_instruction_cache();
 166 }
 167 
 168 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
 169 {
 170         unsigned long addr;
 171         unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
 172 
 173         /* Pin in enough TLBs to cover any lowmem not covered by the
 174          * initial 256M mapping established in head_44x.S */
 175         for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
 176              addr += PPC_PIN_SIZE) {
 177                 if (mmu_has_feature(MMU_FTR_TYPE_47x))
 178                         ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
 179                 else
 180                         ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
 181         }
 182         if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
 183                 ppc47x_update_boltmap();
 184 
 185 #ifdef DEBUG
 186                 {
 187                         int i;
 188 
 189                         printk(KERN_DEBUG "bolted entries: ");
 190                         for (i = 0; i < 255; i++) {
 191                                 if (test_bit(i, tlb_47x_boltmap))
 192                                         printk("%d ", i);
 193                         }
 194                         printk("\n");
 195                 }
 196 #endif /* DEBUG */
 197         }
 198         return total_lowmem;
 199 }
 200 
 201 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 202                                 phys_addr_t first_memblock_size)
 203 {
 204         u64 size;
 205 
 206 #ifndef CONFIG_NONSTATIC_KERNEL
 207         /* We don't currently support the first MEMBLOCK not mapping 0
 208          * physical on those processors
 209          */
 210         BUG_ON(first_memblock_base != 0);
 211 #endif
 212 
 213         /* 44x has a 256M TLB entry pinned at boot */
 214         size = (min_t(u64, first_memblock_size, PPC_PIN_SIZE));
 215         memblock_set_current_limit(first_memblock_base + size);
 216 }
 217 
 218 #ifdef CONFIG_SMP
 219 void __init mmu_init_secondary(int cpu)
 220 {
 221         unsigned long addr;
 222         unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
 223 
 224         /* Pin in enough TLBs to cover any lowmem not covered by the
 225          * initial 256M mapping established in head_44x.S
 226          *
 227          * WARNING: This is called with only the first 256M of the
 228          * linear mapping in the TLB and we can't take faults yet
 229          * so beware of what this code uses. It runs off a temporary
 230          * stack. current (r2) isn't initialized, smp_processor_id()
 231          * will not work, current thread info isn't accessible, ...
 232          */
 233         for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
 234              addr += PPC_PIN_SIZE) {
 235                 if (mmu_has_feature(MMU_FTR_TYPE_47x))
 236                         ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
 237                 else
 238                         ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
 239         }
 240 }
 241 #endif /* CONFIG_SMP */
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root/arch/powerpc/mm/nohash/44x.c

DEFINITIONS
