config_regs 106 drivers/atm/solos-pci.c void __iomem *config_regs; config_regs 527 drivers/atm/solos-pci.c data32 = ioread32(card->config_regs + GPIO_STATUS); config_regs 530 drivers/atm/solos-pci.c iowrite32(data32, card->config_regs + GPIO_STATUS); config_regs 533 drivers/atm/solos-pci.c iowrite32(data32, card->config_regs + GPIO_STATUS); config_regs 548 drivers/atm/solos-pci.c data32 = ioread32(card->config_regs + GPIO_STATUS); config_regs 561 drivers/atm/solos-pci.c data32 = ioread32(card->config_regs + GPIO_STATUS); config_regs 683 drivers/atm/solos-pci.c iowrite32(DRIVER_VERSION, card->config_regs + DRIVER_VER); config_regs 690 drivers/atm/solos-pci.c iowrite32(1, card->config_regs + FPGA_MODE); config_regs 691 drivers/atm/solos-pci.c (void) ioread32(card->config_regs + FPGA_MODE); config_regs 698 drivers/atm/solos-pci.c iowrite32((chip * 2), card->config_regs + FLASH_MODE); config_regs 701 drivers/atm/solos-pci.c iowrite32(1, card->config_regs + WRITE_FLASH); config_regs 702 drivers/atm/solos-pci.c wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY)); config_regs 708 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + WRITE_FLASH); config_regs 712 drivers/atm/solos-pci.c iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE); config_regs 728 drivers/atm/solos-pci.c iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK); config_regs 729 drivers/atm/solos-pci.c iowrite32(1, card->config_regs + WRITE_FLASH); config_regs 730 drivers/atm/solos-pci.c wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY)); config_regs 734 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + WRITE_FLASH); config_regs 735 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + FPGA_MODE); config_regs 736 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + FLASH_MODE); config_regs 746 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + IRQ_CLEAR); config_regs 880 drivers/atm/solos-pci.c card->config_regs + RX_DMA_ADDR(port)); config_regs 892 drivers/atm/solos-pci.c iowrite32(rx_done, card->config_regs + FLAGS_ADDR); config_regs 1060 drivers/atm/solos-pci.c card_flags = ioread32(card->config_regs + FLAGS_ADDR); config_regs 1098 drivers/atm/solos-pci.c card->config_regs + TX_DMA_ADDR(port)); config_regs 1131 drivers/atm/solos-pci.c iowrite32(tx_started, card->config_regs + FLAGS_ADDR); config_regs 1227 drivers/atm/solos-pci.c card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE); config_regs 1228 drivers/atm/solos-pci.c if (!card->config_regs) { config_regs 1241 drivers/atm/solos-pci.c iowrite32(1, card->config_regs + FPGA_MODE); config_regs 1242 drivers/atm/solos-pci.c ioread32(card->config_regs + FPGA_MODE); config_regs 1244 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + FPGA_MODE); config_regs 1245 drivers/atm/solos-pci.c ioread32(card->config_regs + FPGA_MODE); config_regs 1248 drivers/atm/solos-pci.c data32 = ioread32(card->config_regs + FPGA_VER); config_regs 1274 drivers/atm/solos-pci.c data32 = ioread32(card->config_regs + PORTS); config_regs 1294 drivers/atm/solos-pci.c iowrite32(0xF0, card->config_regs + FLAGS_ADDR); config_regs 1313 drivers/atm/solos-pci.c iowrite32(1, card->config_regs + IRQ_EN_ADDR); config_regs 1338 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + IRQ_EN_ADDR); config_regs 1346 drivers/atm/solos-pci.c pci_iounmap(dev, card->config_regs); config_regs 1439 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + IRQ_EN_ADDR); config_regs 1442 drivers/atm/solos-pci.c iowrite32(1, card->config_regs + FPGA_MODE); config_regs 1443 drivers/atm/solos-pci.c (void)ioread32(card->config_regs + FPGA_MODE); config_regs 1456 drivers/atm/solos-pci.c iowrite32(0, card->config_regs + FPGA_MODE); config_regs 1457 drivers/atm/solos-pci.c (void)ioread32(card->config_regs + FPGA_MODE); config_regs 1460 drivers/atm/solos-pci.c pci_iounmap(dev, card->config_regs); config_regs 591 drivers/char/pcmcia/synclink_cs.c link->config_regs = PRESENT_OPTION; config_regs 238 drivers/char/xilinx_hwicap/xilinx_hwicap.c buffer[index++] = hwicap_type_1_write(drvdata->config_regs->CMD) | 1; config_regs 342 drivers/char/xilinx_hwicap/xilinx_hwicap.c drvdata, drvdata->config_regs->IDCODE, &idcode); config_regs 605 drivers/char/xilinx_hwicap/xilinx_hwicap.c const struct config_registers *config_regs) config_regs 672 drivers/char/xilinx_hwicap/xilinx_hwicap.c drvdata->config_regs = config_regs; config_regs 57 drivers/char/xilinx_hwicap/xilinx_hwicap.h const struct config_registers *config_regs; config_regs 42 drivers/gpio/gpio-sch311x.c unsigned short *config_regs; /* pointer to definition below */ config_regs 53 drivers/gpio/gpio-sch311x.c unsigned short config_regs[8]; config_regs 62 drivers/gpio/gpio-sch311x.c .config_regs = {0x23, 0x24, 0x25, 0x26, 0x27, 0x29, 0x2a, 0x2b}, config_regs 67 drivers/gpio/gpio-sch311x.c .config_regs = {0x00, 0x2c, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x32}, config_regs 72 drivers/gpio/gpio-sch311x.c .config_regs = {0x33, 0x34, 0x35, 0x36, 0x37, 0x00, 0x39, 0x3a}, config_regs 77 drivers/gpio/gpio-sch311x.c .config_regs = {0x3b, 0x00, 0x3d, 0x00, 0x6e, 0x6f, 0x72, 0x73}, config_regs 82 drivers/gpio/gpio-sch311x.c .config_regs = {0x3f, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46}, config_regs 87 drivers/gpio/gpio-sch311x.c .config_regs = {0x47, 0x48, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59}, config_regs 136 drivers/gpio/gpio-sch311x.c if (block->config_regs[offset] == 0) /* GPIO is not available */ config_regs 139 drivers/gpio/gpio-sch311x.c if (!request_region(block->runtime_reg + block->config_regs[offset], config_regs 142 drivers/gpio/gpio-sch311x.c block->runtime_reg + block->config_regs[offset]); config_regs 152 drivers/gpio/gpio-sch311x.c if (block->config_regs[offset] == 0) /* GPIO is not available */ config_regs 155 drivers/gpio/gpio-sch311x.c release_region(block->runtime_reg + block->config_regs[offset], 1); config_regs 197 drivers/gpio/gpio-sch311x.c data = inb(block->runtime_reg + block->config_regs[offset]); config_regs 199 drivers/gpio/gpio-sch311x.c outb(data, block->runtime_reg + block->config_regs[offset]); config_regs 213 drivers/gpio/gpio-sch311x.c data = inb(block->runtime_reg + block->config_regs[offset]); config_regs 215 drivers/gpio/gpio-sch311x.c outb(data, block->runtime_reg + block->config_regs[offset]); config_regs 228 drivers/gpio/gpio-sch311x.c data = inb(block->runtime_reg + block->config_regs[offset]); config_regs 244 drivers/gpio/gpio-sch311x.c data = inb(block->runtime_reg + block->config_regs[offset]); config_regs 246 drivers/gpio/gpio-sch311x.c outb(data, block->runtime_reg + block->config_regs[offset]); config_regs 251 drivers/gpio/gpio-sch311x.c data = inb(block->runtime_reg + block->config_regs[offset]); config_regs 253 drivers/gpio/gpio-sch311x.c outb(data, block->runtime_reg + block->config_regs[offset]); config_regs 301 drivers/gpio/gpio-sch311x.c block->config_regs = sch311x_gpio_blocks[i].config_regs; config_regs 413 drivers/gpu/drm/amd/amdgpu/kv_dpm.c const struct kv_pt_config_reg *config_regs = cac_config_regs; config_regs 417 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (config_regs == NULL) config_regs 420 drivers/gpu/drm/amd/amdgpu/kv_dpm.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 421 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (config_regs->type == KV_CONFIGREG_CACHE) { config_regs 422 drivers/gpu/drm/amd/amdgpu/kv_dpm.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 424 drivers/gpu/drm/amd/amdgpu/kv_dpm.c switch (config_regs->type) { config_regs 426 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data = RREG32_SMC(config_regs->offset); config_regs 429 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data = RREG32_DIDT(config_regs->offset); config_regs 432 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data = RREG32(config_regs->offset); config_regs 436 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data &= ~config_regs->mask; config_regs 437 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 441 drivers/gpu/drm/amd/amdgpu/kv_dpm.c switch (config_regs->type) { config_regs 443 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_SMC(config_regs->offset, data); config_regs 446 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32_DIDT(config_regs->offset, data); config_regs 449 drivers/gpu/drm/amd/amdgpu/kv_dpm.c WREG32(config_regs->offset, data); config_regs 453 drivers/gpu/drm/amd/amdgpu/kv_dpm.c config_regs++; config_regs 2840 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_cac_config_reg *config_regs = cac_config_regs; config_regs 2843 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (!config_regs) config_regs 2846 drivers/gpu/drm/amd/amdgpu/si_dpm.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 2847 drivers/gpu/drm/amd/amdgpu/si_dpm.c switch (config_regs->type) { config_regs 2849 drivers/gpu/drm/amd/amdgpu/si_dpm.c offset = SMC_CG_IND_START + config_regs->offset; config_regs 2854 drivers/gpu/drm/amd/amdgpu/si_dpm.c data = RREG32(config_regs->offset); config_regs 2858 drivers/gpu/drm/amd/amdgpu/si_dpm.c data &= ~config_regs->mask; config_regs 2859 drivers/gpu/drm/amd/amdgpu/si_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 2861 drivers/gpu/drm/amd/amdgpu/si_dpm.c switch (config_regs->type) { config_regs 2863 drivers/gpu/drm/amd/amdgpu/si_dpm.c offset = SMC_CG_IND_START + config_regs->offset; config_regs 2868 drivers/gpu/drm/amd/amdgpu/si_dpm.c WREG32(config_regs->offset, data); config_regs 2871 drivers/gpu/drm/amd/amdgpu/si_dpm.c config_regs++; config_regs 898 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c const struct gpu_pt_config_reg *config_regs = cac_config_regs; config_regs 902 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL); config_regs 904 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 905 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c if (config_regs->type == GPU_CONFIGREG_CACHE) config_regs 906 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 908 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c switch (config_regs->type) { config_regs 910 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset); config_regs 914 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); config_regs 918 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); config_regs 922 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data = cgs_read_register(hwmgr->device, config_regs->offset); config_regs 926 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data &= ~config_regs->mask; config_regs 927 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 930 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c switch (config_regs->type) { config_regs 932 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data); config_regs 936 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); config_regs 940 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); config_regs 944 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cgs_write_register(hwmgr->device, config_regs->offset, data); config_regs 950 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c config_regs++; config_regs 799 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type) config_regs 803 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL); config_regs 805 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 808 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); config_regs 809 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; config_regs 810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 811 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); config_regs 814 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); config_regs 815 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; config_regs 816 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 817 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); config_regs 820 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset); config_regs 821 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; config_regs 822 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 823 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data); config_regs 829 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c config_regs++; config_regs 835 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs) config_regs 839 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 840 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data = cgs_read_register(hwmgr->device, config_regs->offset); config_regs 841 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; config_regs 842 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 843 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c cgs_write_register(hwmgr->device, config_regs->offset, data); config_regs 844 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c config_regs++; config_regs 46 drivers/gpu/drm/mediatek/mtk_drm_crtc.c void __iomem *config_regs; config_regs 263 drivers/gpu/drm/mediatek/mtk_drm_crtc.c mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, config_regs 312 drivers/gpu/drm/mediatek/mtk_drm_crtc.c mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, config_regs 570 drivers/gpu/drm/mediatek/mtk_drm_crtc.c mtk_crtc->config_regs = priv->config_regs; config_regs 334 drivers/gpu/drm/mediatek/mtk_drm_ddp.c static void mtk_ddp_sout_sel(void __iomem *config_regs, config_regs 340 drivers/gpu/drm/mediatek/mtk_drm_ddp.c config_regs + DISP_REG_CONFIG_OUT_SEL); config_regs 343 drivers/gpu/drm/mediatek/mtk_drm_ddp.c config_regs + DISP_REG_CONFIG_OUT_SEL); config_regs 345 drivers/gpu/drm/mediatek/mtk_drm_ddp.c config_regs + DISP_REG_CONFIG_DSI_SEL); config_regs 347 drivers/gpu/drm/mediatek/mtk_drm_ddp.c config_regs + DISP_REG_CONFIG_DPI_SEL); config_regs 351 drivers/gpu/drm/mediatek/mtk_drm_ddp.c void mtk_ddp_add_comp_to_path(void __iomem *config_regs, config_regs 359 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) | value; config_regs 360 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); config_regs 363 drivers/gpu/drm/mediatek/mtk_drm_ddp.c mtk_ddp_sout_sel(config_regs, cur, next); config_regs 367 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) | value; config_regs 368 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); config_regs 372 drivers/gpu/drm/mediatek/mtk_drm_ddp.c void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, config_regs 380 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) & ~value; config_regs 381 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); config_regs 386 drivers/gpu/drm/mediatek/mtk_drm_ddp.c reg = readl_relaxed(config_regs + addr) & ~value; config_regs 387 drivers/gpu/drm/mediatek/mtk_drm_ddp.c writel_relaxed(reg, config_regs + addr); config_regs 15 drivers/gpu/drm/mediatek/mtk_drm_ddp.h void mtk_ddp_add_comp_to_path(void __iomem *config_regs, config_regs 18 drivers/gpu/drm/mediatek/mtk_drm_ddp.h void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, config_regs 503 drivers/gpu/drm/mediatek/mtk_drm_drv.c private->config_regs = devm_ioremap_resource(dev, mem); config_regs 504 drivers/gpu/drm/mediatek/mtk_drm_drv.c if (IS_ERR(private->config_regs)) { config_regs 505 drivers/gpu/drm/mediatek/mtk_drm_drv.c ret = PTR_ERR(private->config_regs); config_regs 42 drivers/gpu/drm/mediatek/mtk_drm_drv.h void __iomem *config_regs; config_regs 571 drivers/gpu/drm/radeon/ci_dpm.c const struct ci_pt_config_reg *config_regs = cac_config_regs; config_regs 575 drivers/gpu/drm/radeon/ci_dpm.c if (config_regs == NULL) config_regs 578 drivers/gpu/drm/radeon/ci_dpm.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 579 drivers/gpu/drm/radeon/ci_dpm.c if (config_regs->type == CISLANDS_CONFIGREG_CACHE) { config_regs 580 drivers/gpu/drm/radeon/ci_dpm.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 582 drivers/gpu/drm/radeon/ci_dpm.c switch (config_regs->type) { config_regs 584 drivers/gpu/drm/radeon/ci_dpm.c data = RREG32_SMC(config_regs->offset); config_regs 587 drivers/gpu/drm/radeon/ci_dpm.c data = RREG32_DIDT(config_regs->offset); config_regs 590 drivers/gpu/drm/radeon/ci_dpm.c data = RREG32(config_regs->offset << 2); config_regs 594 drivers/gpu/drm/radeon/ci_dpm.c data &= ~config_regs->mask; config_regs 595 drivers/gpu/drm/radeon/ci_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 598 drivers/gpu/drm/radeon/ci_dpm.c switch (config_regs->type) { config_regs 600 drivers/gpu/drm/radeon/ci_dpm.c WREG32_SMC(config_regs->offset, data); config_regs 603 drivers/gpu/drm/radeon/ci_dpm.c WREG32_DIDT(config_regs->offset, data); config_regs 606 drivers/gpu/drm/radeon/ci_dpm.c WREG32(config_regs->offset << 2, data); config_regs 611 drivers/gpu/drm/radeon/ci_dpm.c config_regs++; config_regs 287 drivers/gpu/drm/radeon/kv_dpm.c const struct kv_pt_config_reg *config_regs = cac_config_regs; config_regs 291 drivers/gpu/drm/radeon/kv_dpm.c if (config_regs == NULL) config_regs 294 drivers/gpu/drm/radeon/kv_dpm.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 295 drivers/gpu/drm/radeon/kv_dpm.c if (config_regs->type == KV_CONFIGREG_CACHE) { config_regs 296 drivers/gpu/drm/radeon/kv_dpm.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 298 drivers/gpu/drm/radeon/kv_dpm.c switch (config_regs->type) { config_regs 300 drivers/gpu/drm/radeon/kv_dpm.c data = RREG32_SMC(config_regs->offset); config_regs 303 drivers/gpu/drm/radeon/kv_dpm.c data = RREG32_DIDT(config_regs->offset); config_regs 306 drivers/gpu/drm/radeon/kv_dpm.c data = RREG32(config_regs->offset << 2); config_regs 310 drivers/gpu/drm/radeon/kv_dpm.c data &= ~config_regs->mask; config_regs 311 drivers/gpu/drm/radeon/kv_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 315 drivers/gpu/drm/radeon/kv_dpm.c switch (config_regs->type) { config_regs 317 drivers/gpu/drm/radeon/kv_dpm.c WREG32_SMC(config_regs->offset, data); config_regs 320 drivers/gpu/drm/radeon/kv_dpm.c WREG32_DIDT(config_regs->offset, data); config_regs 323 drivers/gpu/drm/radeon/kv_dpm.c WREG32(config_regs->offset << 2, data); config_regs 327 drivers/gpu/drm/radeon/kv_dpm.c config_regs++; config_regs 2741 drivers/gpu/drm/radeon/si_dpm.c const struct si_cac_config_reg *config_regs = cac_config_regs; config_regs 2744 drivers/gpu/drm/radeon/si_dpm.c if (!config_regs) config_regs 2747 drivers/gpu/drm/radeon/si_dpm.c while (config_regs->offset != 0xFFFFFFFF) { config_regs 2748 drivers/gpu/drm/radeon/si_dpm.c switch (config_regs->type) { config_regs 2750 drivers/gpu/drm/radeon/si_dpm.c offset = SMC_CG_IND_START + config_regs->offset; config_regs 2755 drivers/gpu/drm/radeon/si_dpm.c data = RREG32(config_regs->offset << 2); config_regs 2759 drivers/gpu/drm/radeon/si_dpm.c data &= ~config_regs->mask; config_regs 2760 drivers/gpu/drm/radeon/si_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); config_regs 2762 drivers/gpu/drm/radeon/si_dpm.c switch (config_regs->type) { config_regs 2764 drivers/gpu/drm/radeon/si_dpm.c offset = SMC_CG_IND_START + config_regs->offset; config_regs 2769 drivers/gpu/drm/radeon/si_dpm.c WREG32(config_regs->offset << 2, data); config_regs 2772 drivers/gpu/drm/radeon/si_dpm.c config_regs++; config_regs 258 drivers/net/can/sja1000/ems_pcmcia.c dev->config_regs = PRESENT_OPTION; config_regs 280 drivers/net/ethernet/8390/axnet_cs.c link->config_regs = 0x63; config_regs 453 drivers/net/ethernet/amd/nmclan_cs.c link->config_regs = PRESENT_OPTION; config_regs 280 drivers/pcmcia/ds.c p_dev->config_regs = cis_config.rmask[0]; config_regs 282 drivers/pcmcia/ds.c p_dev->config_regs); config_regs 287 drivers/pcmcia/ds.c p_dev->config_regs = 0; config_regs 521 drivers/pcmcia/pcmcia_resource.c if (!(p_dev->config_regs & PRESENT_STATUS)) config_regs 530 drivers/pcmcia/pcmcia_resource.c p_dev->config_regs |= PRESENT_EXT_STATUS; config_regs 538 drivers/pcmcia/pcmcia_resource.c p_dev->vpp, flags, p_dev->config_base, p_dev->config_regs, config_regs 543 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_COPY) { config_regs 548 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_PIN_REPLACE) { config_regs 553 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_OPTION) { config_regs 559 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_IOBASE_0) config_regs 568 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_STATUS) config_regs 571 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_EXT_STATUS) config_regs 575 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_IOBASE_0) { config_regs 581 drivers/pcmcia/pcmcia_resource.c if (p_dev->config_regs & PRESENT_IOSIZE) { config_regs 101 drivers/scsi/pcmcia/aha152x_stub.c link->config_regs = PRESENT_OPTION; config_regs 37 drivers/scsi/pcmcia/fdomain_cs.c link->config_regs = PRESENT_OPTION; config_regs 158 drivers/scsi/pcmcia/qlogic_stub.c link->config_regs = PRESENT_OPTION; config_regs 49 drivers/staging/isdn/avm/avm_cs.c p_dev->config_regs = PRESENT_OPTION; config_regs 113 include/pcmcia/ds.h unsigned int config_regs; /* PRESENT_ flags below */ config_regs 134 sound/pcmcia/pdaudiocf/pdaudiocf.c link->config_regs = PRESENT_OPTION; config_regs 156 sound/pcmcia/vx/vxpocket.c link->config_regs = PRESENT_OPTION; config_regs 64 sound/soc/ti/davinci-mcasp.c u32 config_regs[ARRAY_SIZE(context_regs)]; config_regs 2388 sound/soc/ti/davinci-mcasp.c context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); config_regs 2414 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);