fuse 327 arch/c6x/platforms/dscr.c u32 vals[10], fuse; fuse 336 arch/c6x/platforms/dscr.c fuse = soc_readl(base + vals[f * 5]); fuse 339 arch/c6x/platforms/dscr.c c6x_fuse_mac[vals[j] - 1] = fuse >> i; fuse 64 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c static u32 get_accel_mask(u32 fuse) fuse 66 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c return (~fuse) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET & fuse 70 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c static u32 get_ae_mask(u32 fuse) fuse 72 drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c return (~fuse) & ADF_C3XXX_ACCELENGINES_MASK; fuse 58 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c static u32 get_accel_mask(u32 fuse) fuse 63 drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c static u32 get_ae_mask(u32 fuse) fuse 69 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c static u32 get_accel_mask(u32 fuse) fuse 71 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c return (~fuse) >> ADF_C62X_ACCELERATORS_REG_OFFSET & fuse 75 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c static u32 get_ae_mask(u32 fuse) fuse 77 drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c return (~fuse) & ADF_C62X_ACCELENGINES_MASK; fuse 58 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c static u32 get_accel_mask(u32 fuse) fuse 63 drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c static u32 get_ae_mask(u32 fuse) fuse 157 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_accel_mask)(uint32_t fuse); fuse 158 drivers/crypto/qat/qat_common/adf_accel_devices.h uint32_t (*get_ae_mask)(uint32_t fuse); fuse 71 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_accel_mask(uint32_t fuse) fuse 73 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & fuse 77 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c static uint32_t get_ae_mask(uint32_t fuse) fuse 79 drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK; fuse 58 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c static u32 get_accel_mask(u32 fuse) fuse 63 drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c static u32 get_ae_mask(u32 fuse) fuse 2423 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct phm_fuses_default fuse; fuse 2436 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) { fuse 2437 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT0_b = fuse.VFT0_b; fuse 2438 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; fuse 2439 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; fuse 2440 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT1_b = fuse.VFT1_b; fuse 2441 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; fuse 2442 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; fuse 2443 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT2_b = fuse.VFT2_b; fuse 2444 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; fuse 2445 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; fuse 312 drivers/gpu/drm/i915/intel_device_info.c u32 fuse; fuse 314 drivers/gpu/drm/i915/intel_device_info.c fuse = I915_READ(CHV_FUSE_GT); fuse 321 drivers/gpu/drm/i915/intel_device_info.c if (!(fuse & CHV_FGT_DISABLE_SS0)) { fuse 323 drivers/gpu/drm/i915/intel_device_info.c ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> fuse 325 drivers/gpu/drm/i915/intel_device_info.c (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> fuse 332 drivers/gpu/drm/i915/intel_device_info.c if (!(fuse & CHV_FGT_DISABLE_SS1)) { fuse 334 drivers/gpu/drm/i915/intel_device_info.c ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> fuse 336 drivers/gpu/drm/i915/intel_device_info.c (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> fuse 139 drivers/gpu/drm/nouveau/include/nvkm/core/device.h struct nvkm_fuse *fuse; fuse 212 drivers/gpu/drm/nouveau/include/nvkm/core/device.h int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **); fuse 819 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 926 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 958 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 990 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1022 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1054 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1086 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1118 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1150 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1184 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1217 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1250 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1282 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1314 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = nv50_fuse_new, fuse 1347 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1384 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1420 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1456 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1493 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1530 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1567 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1603 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1638 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1674 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1713 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1752 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1789 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1816 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1854 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1892 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1930 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gf100_fuse_new, fuse 1968 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2002 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2035 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2070 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2105 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2139 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2166 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2202 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2238 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2274 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2310 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2346 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2380 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2406 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2447 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2482 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2517 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2552 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2587 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .fuse = gm107_fuse_new, fuse 2648 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(FUSE , device->fuse , &device->fuse->subdev); fuse 3154 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(NVKM_SUBDEV_FUSE , fuse); fuse 27 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c nvkm_fuse_read(struct nvkm_fuse *fuse, u32 addr) fuse 29 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c return fuse->func->read(fuse, addr); fuse 47 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c struct nvkm_fuse *fuse; fuse 48 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c if (!(fuse = *pfuse = kzalloc(sizeof(*fuse), GFP_KERNEL))) fuse 50 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c nvkm_subdev_ctor(&nvkm_fuse, device, index, &fuse->subdev); fuse 51 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c fuse->func = func; fuse 52 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.c spin_lock_init(&fuse->lock); fuse 27 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c gf100_fuse_read(struct nvkm_fuse *fuse, u32 addr) fuse 29 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c struct nvkm_device *device = fuse->subdev.device; fuse 34 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c spin_lock_irqsave(&fuse->lock, flags); fuse 40 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.c spin_unlock_irqrestore(&fuse->lock, flags); fuse 27 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c gm107_fuse_read(struct nvkm_fuse *fuse, u32 addr) fuse 29 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.c struct nvkm_device *device = fuse->subdev.device; fuse 27 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c nv50_fuse_read(struct nvkm_fuse *fuse, u32 addr) fuse 29 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c struct nvkm_device *device = fuse->subdev.device; fuse 34 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c spin_lock_irqsave(&fuse->lock, flags); fuse 38 drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.c spin_unlock_irqrestore(&fuse->lock, flags); fuse 61 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001)) fuse 34 drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) fuse 46 drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.c if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) { fuse 32 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c struct nvkm_fuse *fuse = device->fuse; fuse 34 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c if (!fuse) fuse 37 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.c return nvkm_fuse_read(fuse, 0x1cc); fuse 32 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c struct nvkm_fuse *fuse = device->fuse; fuse 34 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c if (!fuse) fuse 37 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.c return nvkm_fuse_read(fuse, 0x3a8); fuse 72 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c struct nvkm_fuse *fuse = device->fuse; fuse 75 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c if (!fuse) fuse 79 drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c ret = nvkm_fuse_read(fuse, 0x3a8); fuse 1344 drivers/net/wireless/ti/wl18xx/main.c u32 fuse; fuse 1352 drivers/net/wireless/ti/wl18xx/main.c ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); fuse 1356 drivers/net/wireless/ti/wl18xx/main.c package_type = (fuse >> WL18XX_PACKAGE_TYPE_OFFSET) & 1; fuse 1358 drivers/net/wireless/ti/wl18xx/main.c ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse); fuse 1362 drivers/net/wireless/ti/wl18xx/main.c pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET; fuse 1363 drivers/net/wireless/ti/wl18xx/main.c rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET; fuse 1366 drivers/net/wireless/ti/wl18xx/main.c metal = (fuse & WL18XX_METAL_VER_MASK) >> fuse 1369 drivers/net/wireless/ti/wl18xx/main.c metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >> fuse 1372 drivers/net/wireless/ti/wl18xx/main.c ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse); fuse 1376 drivers/net/wireless/ti/wl18xx/main.c rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET; fuse 216 drivers/phy/tegra/xusb-tegra124.c struct tegra124_xusb_fuse_calibration fuse; fuse 503 drivers/phy/tegra/xusb-tegra124.c value |= (priv->fuse.hs_squelch_level << fuse 526 drivers/phy/tegra/xusb-tegra124.c value |= (priv->fuse.hs_curr_level[index] + fuse 543 drivers/phy/tegra/xusb-tegra124.c value |= (priv->fuse.hs_term_range_adj << fuse 545 drivers/phy/tegra/xusb-tegra124.c (priv->fuse.hs_iref_cap << fuse 1656 drivers/phy/tegra/xusb-tegra124.c tegra124_xusb_read_fuse_calibration(struct tegra124_xusb_fuse_calibration *fuse) fuse 1666 drivers/phy/tegra/xusb-tegra124.c for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { fuse 1667 drivers/phy/tegra/xusb-tegra124.c fuse->hs_curr_level[i] = fuse 1671 drivers/phy/tegra/xusb-tegra124.c fuse->hs_iref_cap = fuse 1674 drivers/phy/tegra/xusb-tegra124.c fuse->hs_term_range_adj = fuse 1677 drivers/phy/tegra/xusb-tegra124.c fuse->hs_squelch_level = fuse 1698 drivers/phy/tegra/xusb-tegra124.c err = tegra124_xusb_read_fuse_calibration(&padctl->fuse); fuse 234 drivers/phy/tegra/xusb-tegra210.c struct tegra210_xusb_fuse_calibration fuse; fuse 969 drivers/phy/tegra/xusb-tegra210.c value |= (priv->fuse.hs_curr_level[index] + fuse 982 drivers/phy/tegra/xusb-tegra210.c value |= (priv->fuse.hs_term_range_adj << fuse 984 drivers/phy/tegra/xusb-tegra210.c (priv->fuse.rpd_ctrl << fuse 1949 drivers/phy/tegra/xusb-tegra210.c tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse) fuse 1959 drivers/phy/tegra/xusb-tegra210.c for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { fuse 1960 drivers/phy/tegra/xusb-tegra210.c fuse->hs_curr_level[i] = fuse 1965 drivers/phy/tegra/xusb-tegra210.c fuse->hs_term_range_adj = fuse 1973 drivers/phy/tegra/xusb-tegra210.c fuse->rpd_ctrl = fuse 1994 drivers/phy/tegra/xusb-tegra210.c err = tegra210_xusb_read_fuse_calibration(&padctl->fuse); fuse 34 drivers/soc/tegra/fuse/fuse-tegra.c static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset) fuse 38 drivers/soc/tegra/fuse/fuse-tegra.c val = fuse->read(fuse, round_down(offset, 4)); fuse 50 drivers/soc/tegra/fuse/fuse-tegra.c struct tegra_fuse *fuse = dev_get_drvdata(dev); fuse 60 drivers/soc/tegra/fuse/fuse-tegra.c buf[i] = fuse_readb(fuse, pos + i); fuse 88 drivers/soc/tegra/fuse/fuse-tegra.c static struct tegra_fuse *fuse = &(struct tegra_fuse) { fuse 120 drivers/soc/tegra/fuse/fuse-tegra.c void __iomem *base = fuse->base; fuse 126 drivers/soc/tegra/fuse/fuse-tegra.c fuse->phys = res->start; fuse 127 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = devm_ioremap_resource(&pdev->dev, res); fuse 128 drivers/soc/tegra/fuse/fuse-tegra.c if (IS_ERR(fuse->base)) { fuse 129 drivers/soc/tegra/fuse/fuse-tegra.c err = PTR_ERR(fuse->base); fuse 130 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = base; fuse 134 drivers/soc/tegra/fuse/fuse-tegra.c fuse->clk = devm_clk_get(&pdev->dev, "fuse"); fuse 135 drivers/soc/tegra/fuse/fuse-tegra.c if (IS_ERR(fuse->clk)) { fuse 136 drivers/soc/tegra/fuse/fuse-tegra.c if (PTR_ERR(fuse->clk) != -EPROBE_DEFER) fuse 138 drivers/soc/tegra/fuse/fuse-tegra.c PTR_ERR(fuse->clk)); fuse 140 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = base; fuse 141 drivers/soc/tegra/fuse/fuse-tegra.c return PTR_ERR(fuse->clk); fuse 144 drivers/soc/tegra/fuse/fuse-tegra.c platform_set_drvdata(pdev, fuse); fuse 145 drivers/soc/tegra/fuse/fuse-tegra.c fuse->dev = &pdev->dev; fuse 147 drivers/soc/tegra/fuse/fuse-tegra.c if (fuse->soc->probe) { fuse 148 drivers/soc/tegra/fuse/fuse-tegra.c err = fuse->soc->probe(fuse); fuse 150 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = base; fuse 155 drivers/soc/tegra/fuse/fuse-tegra.c if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size, fuse 156 drivers/soc/tegra/fuse/fuse-tegra.c fuse->soc->info)) fuse 177 drivers/soc/tegra/fuse/fuse-tegra.c unsigned int offset = fuse->soc->info->spare + spare * 4; fuse 179 drivers/soc/tegra/fuse/fuse-tegra.c return fuse->read_early(fuse, offset) & 1; fuse 184 drivers/soc/tegra/fuse/fuse-tegra.c return fuse->read_early(fuse, offset); fuse 189 drivers/soc/tegra/fuse/fuse-tegra.c if (!fuse->read) fuse 192 drivers/soc/tegra/fuse/fuse-tegra.c *value = fuse->read(fuse, offset); fuse 268 drivers/soc/tegra/fuse/fuse-tegra.c fuse->soc = &tegra20_fuse_soc; fuse 274 drivers/soc/tegra/fuse/fuse-tegra.c fuse->soc = &tegra30_fuse_soc; fuse 280 drivers/soc/tegra/fuse/fuse-tegra.c fuse->soc = &tegra114_fuse_soc; fuse 286 drivers/soc/tegra/fuse/fuse-tegra.c fuse->soc = &tegra124_fuse_soc; fuse 311 drivers/soc/tegra/fuse/fuse-tegra.c fuse->soc = match->data; fuse 326 drivers/soc/tegra/fuse/fuse-tegra.c fuse->base = ioremap_nocache(regs.start, resource_size(®s)); fuse 327 drivers/soc/tegra/fuse/fuse-tegra.c if (!fuse->base) { fuse 332 drivers/soc/tegra/fuse/fuse-tegra.c fuse->soc->init(fuse); fuse 29 drivers/soc/tegra/fuse/fuse-tegra20.c static u32 tegra20_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset) fuse 31 drivers/soc/tegra/fuse/fuse-tegra20.c return readl_relaxed(fuse->base + FUSE_BEGIN + offset); fuse 36 drivers/soc/tegra/fuse/fuse-tegra20.c struct tegra_fuse *fuse = args; fuse 38 drivers/soc/tegra/fuse/fuse-tegra20.c complete(&fuse->apbdma.wait); fuse 41 drivers/soc/tegra/fuse/fuse-tegra20.c static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset) fuse 49 drivers/soc/tegra/fuse/fuse-tegra20.c mutex_lock(&fuse->apbdma.lock); fuse 51 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset; fuse 53 drivers/soc/tegra/fuse/fuse-tegra20.c err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config); fuse 57 drivers/soc/tegra/fuse/fuse-tegra20.c dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan, fuse 58 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.phys, fuse 65 drivers/soc/tegra/fuse/fuse-tegra20.c dma_desc->callback_param = fuse; fuse 67 drivers/soc/tegra/fuse/fuse-tegra20.c reinit_completion(&fuse->apbdma.wait); fuse 69 drivers/soc/tegra/fuse/fuse-tegra20.c clk_prepare_enable(fuse->clk); fuse 72 drivers/soc/tegra/fuse/fuse-tegra20.c dma_async_issue_pending(fuse->apbdma.chan); fuse 73 drivers/soc/tegra/fuse/fuse-tegra20.c time_left = wait_for_completion_timeout(&fuse->apbdma.wait, fuse 77 drivers/soc/tegra/fuse/fuse-tegra20.c dmaengine_terminate_all(fuse->apbdma.chan); fuse 79 drivers/soc/tegra/fuse/fuse-tegra20.c value = *fuse->apbdma.virt; fuse 81 drivers/soc/tegra/fuse/fuse-tegra20.c clk_disable_unprepare(fuse->clk); fuse 84 drivers/soc/tegra/fuse/fuse-tegra20.c mutex_unlock(&fuse->apbdma.lock); fuse 95 drivers/soc/tegra/fuse/fuse-tegra20.c static int tegra20_fuse_probe(struct tegra_fuse *fuse) fuse 102 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.chan = dma_request_channel(mask, dma_filter, NULL); fuse 103 drivers/soc/tegra/fuse/fuse-tegra20.c if (!fuse->apbdma.chan) fuse 106 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32), fuse 107 drivers/soc/tegra/fuse/fuse-tegra20.c &fuse->apbdma.phys, fuse 109 drivers/soc/tegra/fuse/fuse-tegra20.c if (!fuse->apbdma.virt) { fuse 110 drivers/soc/tegra/fuse/fuse-tegra20.c dma_release_channel(fuse->apbdma.chan); fuse 114 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; fuse 115 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; fuse 116 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.config.src_maxburst = 1; fuse 117 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.config.dst_maxburst = 1; fuse 118 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.config.direction = DMA_DEV_TO_MEM; fuse 119 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.config.device_fc = false; fuse 121 drivers/soc/tegra/fuse/fuse-tegra20.c init_completion(&fuse->apbdma.wait); fuse 122 drivers/soc/tegra/fuse/fuse-tegra20.c mutex_init(&fuse->apbdma.lock); fuse 123 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->read = tegra20_fuse_read; fuse 153 drivers/soc/tegra/fuse/fuse-tegra20.c static void __init tegra20_fuse_init(struct tegra_fuse *fuse) fuse 155 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->read_early = tegra20_fuse_read_early; fuse 158 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->soc->speedo_init(&tegra_sku_info); fuse 40 drivers/soc/tegra/fuse/fuse-tegra30.c static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset) fuse 42 drivers/soc/tegra/fuse/fuse-tegra30.c if (WARN_ON(!fuse->base)) fuse 45 drivers/soc/tegra/fuse/fuse-tegra30.c return readl_relaxed(fuse->base + FUSE_BEGIN + offset); fuse 48 drivers/soc/tegra/fuse/fuse-tegra30.c static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset) fuse 53 drivers/soc/tegra/fuse/fuse-tegra30.c err = clk_prepare_enable(fuse->clk); fuse 55 drivers/soc/tegra/fuse/fuse-tegra30.c dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err); fuse 59 drivers/soc/tegra/fuse/fuse-tegra30.c value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); fuse 61 drivers/soc/tegra/fuse/fuse-tegra30.c clk_disable_unprepare(fuse->clk); fuse 88 drivers/soc/tegra/fuse/fuse-tegra30.c static void __init tegra30_fuse_init(struct tegra_fuse *fuse) fuse 90 drivers/soc/tegra/fuse/fuse-tegra30.c fuse->read_early = tegra30_fuse_read_early; fuse 91 drivers/soc/tegra/fuse/fuse-tegra30.c fuse->read = tegra30_fuse_read; fuse 95 drivers/soc/tegra/fuse/fuse-tegra30.c if (fuse->soc->speedo_init) fuse 96 drivers/soc/tegra/fuse/fuse-tegra30.c fuse->soc->speedo_init(&tegra_sku_info); fuse 19 drivers/soc/tegra/fuse/fuse.h u32 (*read)(struct tegra_fuse *fuse, unsigned int offset); fuse 25 drivers/soc/tegra/fuse/fuse.h void (*init)(struct tegra_fuse *fuse); fuse 27 drivers/soc/tegra/fuse/fuse.h int (*probe)(struct tegra_fuse *fuse); fuse 38 drivers/soc/tegra/fuse/fuse.h u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset); fuse 39 drivers/soc/tegra/fuse/fuse.h u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);