max_offset 285 arch/arm/mach-omap2/control.c u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; max_offset 291 arch/arm/mach-omap2/control.c for ( ; offset <= max_offset; offset += 0x4) max_offset 883 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c u64 min_offset, u64 max_offset) max_offset 892 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c if (WARN_ON_ONCE(min_offset > max_offset)) max_offset 916 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c if (max_offset != 0) { max_offset 918 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c WARN_ON_ONCE(max_offset < max_offset 934 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c lpfn = max_offset >> PAGE_SHIFT; max_offset 252 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h u64 min_offset, u64 max_offset); max_offset 3937 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c int max_offset) max_offset 3948 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c BUG_ON(*offset_count >= max_offset); max_offset 516 drivers/gpu/drm/i915/selftests/i915_vma.c unsigned int n, max_offset; max_offset 518 drivers/gpu/drm/i915/selftests/i915_vma.c max_offset = max(a->stride * a->height, max_offset 520 drivers/gpu/drm/i915/selftests/i915_vma.c GEM_BUG_ON(max_offset > max_pages); max_offset 521 drivers/gpu/drm/i915/selftests/i915_vma.c max_offset = max_pages - max_offset; max_offset 527 drivers/gpu/drm/i915/selftests/i915_vma.c for_each_prime_number_from(view.rotated.plane[0].offset, 0, max_offset) { max_offset 528 drivers/gpu/drm/i915/selftests/i915_vma.c for_each_prime_number_from(view.rotated.plane[1].offset, 0, max_offset) { max_offset 328 drivers/gpu/drm/radeon/radeon_object.c int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, max_offset 342 drivers/gpu/drm/radeon/radeon_object.c if (max_offset != 0) { max_offset 349 drivers/gpu/drm/radeon/radeon_object.c WARN_ON_ONCE(max_offset < max_offset 365 drivers/gpu/drm/radeon/radeon_object.c (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) max_offset 369 drivers/gpu/drm/radeon/radeon_object.c bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; max_offset 137 drivers/gpu/drm/radeon/radeon_object.h u64 max_offset, u64 *gpu_addr); max_offset 181 drivers/media/pci/ivtv/ivtvfb.c unsigned long max_offset; max_offset 214 drivers/media/pci/ivtv/ivtvfb.c osd->max_offset = oi->display_width * oi->display_height * 4; max_offset 154 drivers/mtd/ftl.c loff_t offset, max_offset; max_offset 158 drivers/mtd/ftl.c max_offset = (0x100000<part->mbd.mtd->size)?0x100000:part->mbd.mtd->size; max_offset 161 drivers/mtd/ftl.c (offset + sizeof(header)) < max_offset; max_offset 173 drivers/mtd/ftl.c if (offset == max_offset) { max_offset 307 drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.c hdr->max_offset = htonl(length); max_offset 54 drivers/net/ethernet/chelsio/libcxgb/libcxgb_ppm.h u32 max_offset; max_offset 2392 drivers/net/usb/r8152.c int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; max_offset 2395 drivers/net/usb/r8152.c if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) max_offset 476 drivers/net/wireless/mediatek/mt76/mt7603/init.c int max_offset, cur_offset; max_offset 485 drivers/net/wireless/mediatek/mt76/mt7603/init.c max_offset = 0; max_offset 488 drivers/net/wireless/mediatek/mt76/mt7603/init.c max_offset = max(max_offset, cur_offset); max_offset 491 drivers/net/wireless/mediatek/mt76/mt7603/init.c target_power += max_offset; max_offset 2901 drivers/pci/pci.c u32 dw0, bei, base, max_offset; max_offset 2944 drivers/pci/pci.c pci_read_config_dword(dev, ent_offset, &max_offset); max_offset 2964 drivers/pci/pci.c end = start + (max_offset | 0x03); max_offset 2967 drivers/pci/pci.c if (max_offset & PCI_EA_IS_64) { max_offset 239 drivers/scsi/53c700.c __u8 max_offset = (hostdata->chip710 max_offset 250 drivers/scsi/53c700.c if(offset > max_offset) { max_offset 252 drivers/scsi/53c700.c offset, max_offset); max_offset 253 drivers/scsi/53c700.c offset = max_offset; max_offset 1988 drivers/scsi/53c700.c int max_offset = hostdata->chip710 max_offset 1994 drivers/scsi/53c700.c if(offset > max_offset) max_offset 1995 drivers/scsi/53c700.c offset = max_offset; max_offset 611 drivers/staging/qlge/qlge_dbg.c u32 max_offset; max_offset 619 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_CAM_WCOUNT; max_offset 623 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_CAM_WCOUNT; max_offset 628 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_CAM_WCOUNT; max_offset 632 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_FC_MAC_WCOUNT; max_offset 636 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_MGMT_MAC_WCOUNT; max_offset 640 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_MGMT_VLAN_WCOUNT; max_offset 644 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_MGMT_V4_WCOUNT; max_offset 648 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_MGMT_V6_WCOUNT; max_offset 652 drivers/staging/qlge/qlge_dbg.c max_offset = MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT; max_offset 657 drivers/staging/qlge/qlge_dbg.c max_offset = 0; max_offset 661 drivers/staging/qlge/qlge_dbg.c for (offset = 0; offset < max_offset; offset++) { max_offset 2022 fs/btrfs/ioctl.c test.offset = sk->max_offset; max_offset 2127 fs/btrfs/ioctl.c test.offset = sk->max_offset; max_offset 259 include/net/cfg80211.h u8 max_offset; max_offset 22 include/scsi/scsi_transport_spi.h int max_offset; max_offset 65 include/scsi/scsi_transport_spi.h #define spi_max_offset(x) (((struct spi_transport_attrs *)&(x)->starget_data)->max_offset) max_offset 475 include/uapi/linux/btrfs.h __u64 max_offset; /* in */ max_offset 88 net/mac80211/he.c he_obss_pd->max_offset = *data++; max_offset 4502 net/wireless/nl80211.c he_obss_pd->max_offset = max_offset 4505 net/wireless/nl80211.c if (he_obss_pd->min_offset >= he_obss_pd->max_offset) max_offset 32 tools/testing/selftests/powerpc/stringloops/memcmp.c static void test_one(char *s1, char *s2, unsigned long max_offset, max_offset 37 tools/testing/selftests/powerpc/stringloops/memcmp.c for (offset = 0; offset < max_offset; offset++) {