priv2 114 arch/powerpc/include/asm/spu.h struct spu_priv2 __iomem *priv2; priv2 233 arch/powerpc/include/asm/spu_csa.h struct spu_priv2_collapsed priv2; priv2 68 arch/powerpc/platforms/cell/spu_base.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 73 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->slb_invalidate_all_W, 0UL); priv2 125 arch/powerpc/platforms/cell/spu_base.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 128 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); priv2 137 arch/powerpc/platforms/cell/spu_base.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 142 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->slb_index_W, slbe); priv2 144 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->slb_esid_RW, 0); priv2 146 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->slb_vsid_RW, slb->vsid); priv2 148 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->slb_esid_RW, slb->esid); priv2 453 arch/powerpc/platforms/cell/spu_base.c struct spu_priv2 __iomem *priv2; priv2 456 arch/powerpc/platforms/cell/spu_base.c priv2 = spu->priv2; priv2 462 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel); priv2 464 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->spu_chnldata_RW, 0); priv2 469 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel); priv2 470 arch/powerpc/platforms/cell/spu_base.c out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count); priv2 62 arch/powerpc/platforms/cell/spu_manage.c iounmap(spu->priv2); priv2 150 arch/powerpc/platforms/cell/spu_manage.c spu->priv2 = spu_map_prop_old(spu, node, "priv2"); priv2 151 arch/powerpc/platforms/cell/spu_manage.c if (!spu->priv2) priv2 232 arch/powerpc/platforms/cell/spu_manage.c ret = spu_map_resource(spu, 2, (void __iomem**)&spu->priv2, NULL); priv2 251 arch/powerpc/platforms/cell/spu_manage.c pr_debug(" priv2 : 0x%p\n", spu->priv2); priv2 333 arch/powerpc/platforms/cell/spu_manage.c spu->priv2, spu->number); priv2 125 arch/powerpc/platforms/cell/spufs/backing_ops.c *data = ctx->csa.priv2.puint_mb_R; priv2 178 arch/powerpc/platforms/cell/spufs/backing_ops.c if (ctx->csa.priv2.spu_cfg_RW & 0x1) priv2 195 arch/powerpc/platforms/cell/spufs/backing_ops.c if (ctx->csa.priv2.spu_cfg_RW & 0x2) priv2 209 arch/powerpc/platforms/cell/spufs/backing_ops.c tmp = ctx->csa.priv2.spu_cfg_RW; priv2 214 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.priv2.spu_cfg_RW = tmp; priv2 220 arch/powerpc/platforms/cell/spufs/backing_ops.c return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0); priv2 228 arch/powerpc/platforms/cell/spufs/backing_ops.c tmp = ctx->csa.priv2.spu_cfg_RW; priv2 233 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.priv2.spu_cfg_RW = tmp; priv2 239 arch/powerpc/platforms/cell/spufs/backing_ops.c return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0); priv2 264 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.priv2.spu_privcntl_RW = val; priv2 368 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND; priv2 1816 arch/powerpc/platforms/cell/spufs/file.c ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING; priv2 1818 arch/powerpc/platforms/cell/spufs/file.c ctx->csa.priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING; priv2 1826 arch/powerpc/platforms/cell/spufs/file.c if (ctx->csa.priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) priv2 1928 arch/powerpc/platforms/cell/spufs/file.c return ctx->csa.priv2.spu_lslr_RW; priv2 2013 arch/powerpc/platforms/cell/spufs/file.c data = ctx->csa.priv2.puint_mb_R; priv2 2094 arch/powerpc/platforms/cell/spufs/file.c info.dma_info_type = ctx->csa.priv2.spu_tag_status_query_RW; priv2 2101 arch/powerpc/platforms/cell/spufs/file.c spuqp = &ctx->csa.priv2.spuq[i]; priv2 2158 arch/powerpc/platforms/cell/spufs/file.c puqp = &ctx->csa.priv2.puq[i]; priv2 2512 arch/powerpc/platforms/cell/spufs/file.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 2515 arch/powerpc/platforms/cell/spufs/file.c mfc_control_RW = in_be64(&priv2->mfc_control_RW); priv2 2520 arch/powerpc/platforms/cell/spufs/file.c mfc_control_RW = csa->priv2.mfc_control_RW; priv2 86 arch/powerpc/platforms/cell/spufs/hw_ops.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 92 arch/powerpc/platforms/cell/spufs/hw_ops.c *data = in_be64(&priv2->puint_mb_R); priv2 137 arch/powerpc/platforms/cell/spufs/hw_ops.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 141 arch/powerpc/platforms/cell/spufs/hw_ops.c tmp = in_be64(&priv2->spu_cfg_RW); priv2 146 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be64(&priv2->spu_cfg_RW, tmp); priv2 152 arch/powerpc/platforms/cell/spufs/hw_ops.c return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0); priv2 158 arch/powerpc/platforms/cell/spufs/hw_ops.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 162 arch/powerpc/platforms/cell/spufs/hw_ops.c tmp = in_be64(&priv2->spu_cfg_RW); priv2 167 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be64(&priv2->spu_cfg_RW, tmp); priv2 173 arch/powerpc/platforms/cell/spufs/hw_ops.c return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0); priv2 198 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be64(&ctx->spu->priv2->spu_privcntl_RW, val); priv2 302 arch/powerpc/platforms/cell/spufs/hw_ops.c struct spu_priv2 __iomem *priv2 = ctx->spu->priv2; priv2 305 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); priv2 104 arch/powerpc/platforms/cell/spufs/run.c mfc_cntl = &ctx->spu->priv2->mfc_control_RW; priv2 169 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 174 arch/powerpc/platforms/cell/spufs/switch.c switch (in_be64(&priv2->mfc_control_RW) & priv2 177 arch/powerpc/platforms/cell/spufs/switch.c POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & priv2 183 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW = priv2 184 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->mfc_control_RW) | priv2 188 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); priv2 189 arch/powerpc/platforms/cell/spufs/switch.c POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & priv2 193 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW = priv2 194 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->mfc_control_RW) & priv2 249 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 259 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW &= ~mask; priv2 260 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask; priv2 265 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 271 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->mfc_control_RW, priv2 335 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 342 arch/powerpc/platforms/cell/spufs/switch.c if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) { priv2 344 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data0_RW = priv2 345 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->puq[i].mfc_cq_data0_RW); priv2 346 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data1_RW = priv2 347 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->puq[i].mfc_cq_data1_RW); priv2 348 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data2_RW = priv2 349 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->puq[i].mfc_cq_data2_RW); priv2 350 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data3_RW = priv2 351 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->puq[i].mfc_cq_data3_RW); priv2 354 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data0_RW = priv2 355 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->spuq[i].mfc_cq_data0_RW); priv2 356 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data1_RW = priv2 357 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->spuq[i].mfc_cq_data1_RW); priv2 358 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data2_RW = priv2 359 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->spuq[i].mfc_cq_data2_RW); priv2 360 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data3_RW = priv2 361 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->spuq[i].mfc_cq_data3_RW); priv2 403 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 409 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_tag_status_query_RW = priv2 410 arch/powerpc/platforms/cell/spufs/switch.c in_be64(&priv2->spu_tag_status_query_RW); priv2 415 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 421 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW); priv2 422 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW); priv2 427 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 433 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW); priv2 458 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 464 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->mfc_control_RW, priv2 472 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 478 arch/powerpc/platforms/cell/spufs/switch.c POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & priv2 513 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 518 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW); priv2 523 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 529 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_privcntl_RW, 0UL); priv2 535 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 540 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW); priv2 545 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 551 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK); priv2 557 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 562 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW); priv2 607 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 612 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R); priv2 617 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 625 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, 1); priv2 626 arch/powerpc/platforms/cell/spufs/switch.c csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW); priv2 631 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, idx); priv2 633 arch/powerpc/platforms/cell/spufs/switch.c csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW); priv2 634 arch/powerpc/platforms/cell/spufs/switch.c csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW); priv2 635 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnldata_RW, 0UL); priv2 636 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, 0UL); priv2 643 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 649 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, 29UL); priv2 651 arch/powerpc/platforms/cell/spufs/switch.c csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW); priv2 653 arch/powerpc/platforms/cell/spufs/switch.c csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW); priv2 655 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, 0UL); priv2 661 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 666 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, 21UL); priv2 668 arch/powerpc/platforms/cell/spufs/switch.c csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW); priv2 674 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 685 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, idx); priv2 687 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); priv2 694 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 700 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE); priv2 736 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND; priv2 964 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 970 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE | priv2 978 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 984 arch/powerpc/platforms/cell/spufs/switch.c POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & priv2 1067 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1076 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, 1); priv2 1077 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnldata_RW, 0UL); priv2 1082 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, idx); priv2 1084 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnldata_RW, 0UL); priv2 1085 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, 0UL); priv2 1092 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1103 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, idx); priv2 1105 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); priv2 1263 arch/powerpc/platforms/cell/spufs/switch.c if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) { priv2 1292 arch/powerpc/platforms/cell/spufs/switch.c csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R; priv2 1312 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1317 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW); priv2 1386 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1392 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); priv2 1418 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1425 arch/powerpc/platforms/cell/spufs/switch.c if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) { priv2 1427 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->puq[i].mfc_cq_data0_RW, priv2 1428 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data0_RW); priv2 1429 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->puq[i].mfc_cq_data1_RW, priv2 1430 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data1_RW); priv2 1431 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->puq[i].mfc_cq_data2_RW, priv2 1432 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data2_RW); priv2 1433 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->puq[i].mfc_cq_data3_RW, priv2 1434 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.puq[i].mfc_cq_data3_RW); priv2 1437 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spuq[i].mfc_cq_data0_RW, priv2 1438 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data0_RW); priv2 1439 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spuq[i].mfc_cq_data1_RW, priv2 1440 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data1_RW); priv2 1441 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spuq[i].mfc_cq_data2_RW, priv2 1442 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data2_RW); priv2 1443 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spuq[i].mfc_cq_data3_RW, priv2 1444 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spuq[i].mfc_cq_data3_RW); priv2 1474 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1479 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_tag_status_query_RW, priv2 1480 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_tag_status_query_RW); priv2 1486 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1492 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW); priv2 1493 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW); priv2 1499 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1504 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW); priv2 1559 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1568 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, idx); priv2 1570 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]); priv2 1571 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]); priv2 1578 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1592 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, idx); priv2 1594 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); priv2 1601 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1606 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW); priv2 1612 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1617 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW); priv2 1642 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1648 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcntptr_RW, 29UL); priv2 1650 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]); priv2 1652 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]); priv2 1674 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1682 arch/powerpc/platforms/cell/spufs/switch.c dummy = in_be64(&priv2->puint_mb_R); priv2 1729 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1734 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW); priv2 1876 arch/powerpc/platforms/cell/spufs/switch.c struct spu_priv2 __iomem *priv2 = spu->priv2; priv2 1888 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_privcntl_RW, 4LL); priv2 1896 arch/powerpc/platforms/cell/spufs/switch.c out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL); priv2 2167 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.spu_lslr_RW = LS_ADDR_MASK; priv2 2168 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE | priv2 123 arch/powerpc/platforms/ps3/spu.c static void _dump_areas(unsigned int spe_id, unsigned long priv2, priv2 128 arch/powerpc/platforms/ps3/spu.c pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2); priv2 177 arch/powerpc/platforms/ps3/spu.c iounmap(spu->priv2); priv2 218 arch/powerpc/platforms/ps3/spu.c spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr, priv2 221 arch/powerpc/platforms/ps3/spu.c if (!spu->priv2) { priv2 229 arch/powerpc/platforms/ps3/spu.c dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2, priv2 4095 arch/powerpc/xmon/xmon.c DUMP_FIELD(spu, "0x%p", priv2); priv2 1983 drivers/usb/gadget/function/uvc_configfs.c void *priv2, void *priv3, priv2 1996 drivers/usb/gadget/function/uvc_configfs.c ret = fun(h, priv2, priv3, 0, UVCG_HEADER); priv2 2000 drivers/usb/gadget/function/uvc_configfs.c ret = fun(f->fmt, priv2, priv3, i++, UVCG_FORMAT); priv2 2006 drivers/usb/gadget/function/uvc_configfs.c ret = fun(frm, priv2, priv3, j++, UVCG_FRAME); priv2 2023 drivers/usb/gadget/function/uvc_configfs.c static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, priv2 2026 drivers/usb/gadget/function/uvc_configfs.c size_t *size = priv2; priv2 2079 drivers/usb/gadget/function/uvc_configfs.c static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, priv2 2082 drivers/usb/gadget/function/uvc_configfs.c void **dest = priv2;