Lines Matching refs:be

18 hypervisor code, or it may just be a handful of instructions for
48 The device tree blob (dtb) must be placed on an 8-byte boundary within
60 therefore requires decompression (gzip etc.) to be performed by the boot
99   little-endian and must be respected.  Where image_size is zero,
100   text_offset can be assumed to be 0x80000.
112 The Image must be placed text_offset bytes from a 2MB aligned base
116 At least image_size bytes from the start of the image must be free for
121 memreserve region in the device tree) will be considered as available to
124 Before jumping into the kernel, the following conditions must be met:
137   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
139   The CPU must be in either EL2 (RECOMMENDED in order to have access to
143   The MMU must be off.
144   Instruction cache may be on or off.
145   The address range corresponding to the loaded kernel image must be
150   operations must be configured and may be enabled.
152   operations (not recommended) must be configured and disabled.
155   CNTFRQ must be programmed with the timer frequency and CNTVOFF must
156   be programmed with a consistent value on all CPUs.  If entering the
161   All CPUs to be booted by the kernel must be part of the same coherency
168   the kernel image will be entered must be initialised by software at a
173     ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
174     ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
176     ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
177     ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
200   device tree) polling their cpu-release-addr location, which must be
201   contained in the reserved region.  A wfe instruction may be inserted
202   to reduce the overhead of the busy-loop and a sev will be issued by
205   value.  The value will be written as a single 64-bit little-endian