Lines Matching refs:and

4 interrupts (PPI), shared processor interrupts (SPI) and software
7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8 Secondary GICs are cascaded into the upward interrupt controller and do not
25   interrupt source.  The type shall be a <u32> and the value shall be 3.
35 	bits[3:0] trigger type and level flags.
44 	DEFINED and as such not guaranteed to be present (most SoC available
45 	in 2014 seem to ignore the setting of this flag and use the hardware
48 - reg : Specifies base physical address(s) and size of the GIC registers. The
49   first region is the GIC distributor register base and size. The 2nd region is
50   the GIC cpu interface register base and size.
57 - cpu-offset	: per-cpu offset within the distributor and cpu interface
81 - reg : Additional regions specifying the base physical address and
83   virtual interface control register base and size. The 2nd additional
84   region is the GIC virtual cpu interface register base and size.
113 - reg		    : GICv2m MSI interface register base and size