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4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
20 cache hierarchy is also out of standby, and then the cpu is allowed to resume
22 driver and is not defined in the DT. The SPM state machine should be
23 configured to execute this state by default and after executing every other
26 Retention: Retention is a low power state where the core is clock gated and
27 the memory and the registers associated with the core are retained. The
30 sequence and would wait for interrupt, before restoring the cpu to execution
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
34 between the time it enters idle and the next known wake up. SPC mode is used
38 core, wait for the interrupt, restore power to the core, and ensure the
40 resume. Applying power and resetting the core causes the core to warmboot
48 itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
52 power modes possible at this state is vast, the exit latency and the residency
69 		and "arm,idle-state".
71 Other required and optional properties are specified in [1].