Lines Matching refs:and

1 This binding is a work-in-progress, and are based on some experimental
6 nodes use a phandle and clock specifier pair to connect clock provider
18 		   with a single clock output and 1 for nodes with multiple
25 		    specific to the clock provider, and is only provided to
29 		    is recommended to omit this property and create a binding
43   "ckil" and the second named "ckih".  Consumer nodes always reference
51 For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
66 clocks:		List of phandle and clock specifier pairs, one pair
88 This represents a device with two clock inputs, named "baud" and "register".
89 The baud clock is connected to output 1 of the &osc device, and the register
114      * and the high frequency switched PLL output for register
126 clock signal, and a UART.
128 * The oscillator is fixed-frequency, and provides one clock output, named "osc".
129 * The PLL is both a clock provider and a clock consumer. It uses the clock
130   signal generated by the external oscillator, and provides two output signals
131   ("pll" and "pll-switched").
132 * The UART has its baud clock connected the external oscillator and its
135 ==Assigned clock parents and rates==
138 and clock frequencies. Such a configuration can be specified in a device tree
139 node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
141 clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
160 In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
163 Configuring a clock's parent and rate through the device node that consumes