Lines Matching refs:pll

104     pll: pll@4c000 {
105         compatible = "vendor,some-pll-interface"
110         clock-output-names = "pll", "pll-switched";
120         clocks = <&osc 0>, <&pll 1>;
131   ("pll" and "pll-switched").
133   register clock connected to the PLL clock (the "pll-switched" signal)
152         clocks = <&osc 0>, <&pll 1>;
155         assigned-clocks = <&clkcon 0>, <&pll 2>;
156         assigned-clock-parents = <&pll 2>;
160 In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
161 the <&pll 2> clock is assigned a frequency value of 460800 Hz.