Lines Matching refs:clock

4 peripheral clocks to be gated to save some power. The clock consumer
5 should specify the desired clock by having the clock ID in its
6 "clocks" phandle cell. The clock ID is directly mapped to the
7 corresponding clock gating control bit in HW to ease manual clock
140 Note: gephy(30) is implemented as a parent clock of ge(2)
164 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
165 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
166 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
167 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
168 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
169 	"marvell,dove-gating-clock" - for Dove SoC clock gating
170 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
172 - #clock-cells : from common clock binding; shall be set to 1
175 - clocks : default parent clock phandle (e.g. tclk)
179 gate_clk: clock-gating-control@d0038 {
180 	compatible = "marvell,dove-gating-clock";
182 	/* default parent clock is tclk */
184 	#clock-cells = <1>;