Lines Matching refs:clock

21 - compatible: Should contain a specific clock block compatible string
22 	and a single chassis clock compatible string.
33 	Chassis clock strings include:
38 	represents the clock register set
39 - clock-frequency: Input system clock frequency
53 Most of the bindings are from the common clock binding[1].
54  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
62 	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
63 		It takes parent's clock-frequency as its clock.
64 	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
65 		It takes parent's clock-frequency as its clock.
66 	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
67 	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
68 - #clock-cells: From common clock binding. The number of cells in a
69 	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
72 	clock-specifier cell may take the following values:
78 - clocks: Should be the phandle of input parent clock
79 - clock-names: From common clock binding, indicates the clock name
80 - clock-output-names: From common clock binding, indicates the names of
82 - reg: Should be the offset and length of clock block base address.
85 Example for clock block and clock provider:
90 		clock-frequency = <133333333>;
96 			#clock-cells = <0>;
98 			clock-output-names = "sysclk";
102 			#clock-cells = <1>;
106 			clock-output-names = "pll0", "pll0-div2";
110 			#clock-cells = <1>;
114 			clock-output-names = "pll1", "pll1-div2";
118 			#clock-cells = <0>;
122 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
123 			clock-output-names = "cmux0";
127 			#clock-cells = <0>;
131 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
132 			clock-output-names = "cmux1";
136 			#clock-cells = <1>;
140 			clock-output-names = "platform-pll", "platform-pll-div2";
145 Example for clock consumer: