Lines Matching refs:clock
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
14 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
15 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
16 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17 "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
18 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
19 "allwinner,sun4i-a10-axi-clk" - for the AXI clock
20 "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
22 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
23 "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
30 "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
36 "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
37 "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
38 "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
39 "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
47 "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
48 "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
58 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
59 "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
64 "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
66 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
74 - reg : shall be the control register address for the clock.
75 - clocks : shall be the input parent clock(s) phandle for the clock. For
78 - #clock-cells : from common clock binding; shall be set to 0 except for
84 - clock-output-names : shall be the corresponding names of the outputs.
85 If the clock module only has one output, the name shall be the
91 The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
99 "clocks" phandle cell. Consumers that are using a gated clock should
100 provide an additional ID in their clock property. This ID is the
102 For the other clocks with "#clock-cells" = 1, the additional ID shall
110 main clock, with the ID 0, and the output and sample clocks, with the
113 The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
120 #clock-cells = <0>;
124 clock-output-names = "osc24M";
128 #clock-cells = <0>;
132 clock-output-names = "pll1";
136 #clock-cells = <1>;
140 clock-output-names = "pll5_ddr", "pll5_other";
144 #clock-cells = <1>;
148 clock-output-names = "pll6", "pll6x2";
152 #clock-cells = <0>;
156 clock-output-names = "cpu";
160 #clock-cells = <1>;
164 clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
168 #clock-cells = <0>;
169 compatible = "fixed-clock";
170 clock-frequency = <25000000>;
171 clock-output-names = "mii_phy_tx";
175 #clock-cells = <0>;
176 compatible = "fixed-clock";
177 clock-frequency = <125000000>;
178 clock-output-names = "gmac_int_tx";
182 #clock-cells = <0>;
186 * The first clock must be fixed at 25MHz;
187 * the second clock must be fixed at 125MHz
190 clock-output-names = "gmac";
197 clock-names = "ahb";
200 #clock-cells = <1>;
202 clock-output-names = "mmc0_config", "mmc1_config",