Lines Matching refs:the
3 This binding uses the common clock binding[1].
8 - compatible : shall be one of the following:
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
14 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
15 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
16 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17 "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
18 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
19 "allwinner,sun4i-a10-axi-clk" - for the AXI clock
20 "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
21 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
22 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
23 "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
24 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
25 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
26 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
27 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
28 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
29 "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
30 "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
31 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
32 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
33 "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
34 "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
35 "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
36 "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
37 "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
38 "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
39 "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
40 "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
41 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
42 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
43 "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
44 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
45 "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
46 "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
47 "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
48 "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
49 "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
50 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
51 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
52 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
53 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
54 "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
55 "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
56 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
57 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
58 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
59 "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
62 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
64 "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
65 "allwinner,sun7i-a20-out-clk" - for the external output clocks
66 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
74 - reg : shall be the control register address for the clock.
75 - clocks : shall be the input parent clock(s) phandle for the clock. For
76 multiplexed clocks, the list order must match the hardware
79 the following compatibles where it shall be set to 1:
84 - clock-output-names : shall be the corresponding names of the outputs.
85 If the clock module only has one output, the name shall be the
93 - resets : shall be the reset control phandle for the mmc block.
95 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
98 Clock consumers should specify the desired clocks they use with a
100 provide an additional ID in their clock property. This ID is the
101 offset of the bit controlling this particular gate in the register.
102 For the other clocks with "#clock-cells" = 1, the additional ID shall
103 refer to the index of the output.
106 is the normal PLL6 output, or "pll6". The second output is rate doubled
109 The "allwinner,*-mmc-clk" clocks have three different outputs: the
110 main clock, with the ID 0, and the output and sample clocks, with the
114 per mmc controller. The number of outputs is determined by the size of
115 the address block, which is related to the overall mmc block.
187 * the second clock must be fixed at 125MHz