Lines Matching refs:be

8 - compatible : shall be one of the following:
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
18 	be the reference clock.
19 - #clock-cells : from common clock binding; shall be set to 0.
22 - clocks : shall be the input parent clock phandle for the clock. This should
23 	be a pll output.
24 - #clock-cells : from common clock binding; shall be set to 0.
36 - enable-reg : shall be the register offset from PMC base for the enable
38 - enable-bit : shall be the bit within enable-reg to enable/disable the clock.
44 - divisor-reg : shall be the register offset from PMC base for the divisor
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f