Lines Matching refs:the
5 many of the peripherals needed to implement a complete computer
7 the system controller chip itself and each of the peripherals
9 prefixed with the string "marvell,", for Marvell Technology Group Ltd.
13 This node is used to represent the system-controller and must be
14 present when the system uses a system controller chip. The top-level
16 devices within the system controller chip. The node name begins
17 with "system-controller" followed by the unit address, which is
18 the base address of the memory-mapped register set for the system
23 - ranges : Describes the translation of system controller addresses
25 - clock-frequency: Contains the main clock frequency for the system
27 - reg : This property defines the address and size of the
28 memory-mapped registers contained within the system controller
29 chip. The address specified in the "reg" property should match
30 the unit address of the system-controller node.
32 devices. This field represents the number of cells needed to
33 represent the address of the memory-mapped registers of devices
34 within the system controller chip.
35 - #size-cells : Size representation for the memory-mapped
36 registers within the system controller chip.
37 - #interrupt-cells : Defines the width of cells used to represent
42 - model : The specific model of the system controller chip. Such
44 - compatible : A string identifying the compatibility identifiers
45 of the system controller chip.
48 controller device that the platform uses. Nodes should not be created
49 for devices which exist on the system controller chip but are not used
74 The MDIO is a bus to which the PHY devices are connected. For each
76 the definition of the PHY node below for an example of how to define
101 and the second level describes up to 3 ethernet nodes within
102 that block. The reason for the multiple levels is that the
103 registers for the node are interleaved within a single set
104 of registers. The "ethernet-block" level describes the
105 shared register set, and the "ethernet" nodes describe ethernet
114 - reg : Offset and length of the register set for this block
117 - clocks : Phandle to the clock control device and gate bit
135 within the silicon block the device uses.
136 - interrupts : <a> where a is the interrupt number for the port.
137 - interrupt-parent : the phandle for the interrupt controller
139 - phy : the phandle for the PHY connected to this ethernet
158 - interrupts : <a> where a is the interrupt number for this phy.
159 - interrupt-parent : the phandle for the interrupt controller that
161 - reg : The ID number for the phy, usually a small integer
174 Represent DMA hardware associated with the MPSC (multiprotocol
179 - reg : Offset and length of the register set for this device
180 - interrupts : <a> where a is the interrupt number for the DMA
182 - interrupt-parent : the phandle for the interrupt controller
197 Represent baud rate generator hardware associated with the MPSC
202 - reg : Offset and length of the register set for this device
203 - clock-src : A value from 0 to 15 which selects the clock
204 source for the baud rate generator. This value corresponds
205 to the CLKS value in the BRGx configuration register. See
206 the mv64x60 User's Manual.
207 - clock-frequence : The frequency (in Hz) of the baud rate
210 firmware) of the baud rate generator.
224 Represent the Serial Communications Unit device hardware.
227 - reg : Offset and length of the register set for this device
237 Represent the Discovery's MPSC routing hardware
240 - reg : Offset and length of the register set for this device
250 Represent the Discovery's MPSC DMA interrupt hardware registers
254 - reg : Offset and length of the register set for this device
264 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
269 - reg : Offset and length of the register set for this device
270 - sdma : the phandle for the SDMA node used by this port
271 - brg : the phandle for the BRG node used by this port
272 - cunit : the phandle for the CUNIT node used by this port
273 - mpscrouting : the phandle for the MPSCROUTING node used by this port
274 - mpscintr : the phandle for the MPSCINTR node used by this port
275 - cell-index : the hardware index of this cell in the MPSC core
278 - interrupts : <a> where a is the interrupt number for the MPSC.
279 - interrupt-parent : the phandle for the interrupt controller
301 Represent the Discovery's watchdog timer hardware
305 - reg : Offset and length of the register set for this device
316 Represent the Discovery's I2C hardware
321 - reg : Offset and length of the register set for this device
322 - interrupts : <a> where a is the interrupt number for the I2C.
323 - interrupt-parent : the phandle for the interrupt controller
337 Represent the Discovery's PIC hardware
343 - reg : Offset and length of the register set for this device
358 Represent the Discovery's MPP hardware
362 - reg : Offset and length of the register set for this device
373 Represent the Discovery's GPP hardware
377 - reg : Offset and length of the register set for this device
388 Represents the Discovery's PCI host bridge device. The properties
389 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
390 1275-1994. A typical value for the compatible property is
439 Represent the Discovery's CPU error handler device.
443 - reg : Offset and length of the register set for this device
444 - interrupts : the interrupt number for this device
445 - interrupt-parent : the phandle for the interrupt controller
459 Represent the Discovery's SRAM controller device.
463 - reg : Offset and length of the register set for this device
464 - interrupts : the interrupt number for this device
465 - interrupt-parent : the phandle for the interrupt controller
479 Represent the Discovery's PCI error handler device.
483 - reg : Offset and length of the register set for this device
484 - interrupts : the interrupt number for this device
485 - interrupt-parent : the phandle for the interrupt controller
499 Represent the Discovery's memory controller device.
503 - reg : Offset and length of the register set for this device
504 - interrupts : the interrupt number for this device
505 - interrupt-parent : the phandle for the interrupt controller