Lines Matching refs:and

5 serial interfaces with frame synchronization such as I2S, AC97, TDM, and
13   - reg			: Offset and length of the register set for the device.
17   - clock-names		: Must include the "bus" for register access and
18 			  "mclk1", "mclk2", "mclk3" for bit clock and frame
23   - dma-names		: Two dmas have to be defined, "tx" and "rx".
41 			  with Rx) which means both the transimitter and the
42 			  receiver will send and receive data by following
43 			  receiver's bit clocks and frame sync clocks.
47 			  means both transimitter and receiver will send and
48 			  receive data by following their own bit clocks and
52 - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
54   transimitter and receiver will send and receive data by following clocks
56 - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.