Lines Matching refs:phy

3 ** Samsung's usb 2.0 phy transceiver
5 The Samsung's usb 2.0 phy transceiver is used for controlling
6 usb 2.0 phy for s3c-hsotg as well as ehci-s5p and ohci-exynos
15 - reg : base physical address of the phy registers and length of memory mapped
23 - reg : base physical address of the phy registers and length of memory mapped
35   interface for usb-phy. It should provide the following information required by
36   usb-phy controller to control phy.
66 ** Samsung's usb 3.0 phy transceiver
68 Starting exynso5250, Samsung's SoC have usb 3.0 phy transceiver
69 which is used for controlling usb 3.0 phy for dwc3-exynos usb 3.0
76 - reg : base physical address of the phy registers and length of memory mapped
91   interface for usb-phy. It should provide the following information required by
92   usb-phy controller to control phy.