Lines Matching refs:A

5 chipset to flush pending writes to the device before any reads are posted.  A
11 A more concrete example from a hypothetical device driver:
14 CPU A:  spin_lock_irqsave(&dev_lock, flags)
15 CPU A:  val = readl(my_status);
16 CPU A:  ...
17 CPU A:  writel(newval, ring_ptr);
18 CPU A:  spin_unlock_irqrestore(&dev_lock, flags)
31 CPU A:  spin_lock_irqsave(&dev_lock, flags)
32 CPU A:  val = readl(my_status);
33 CPU A:  ...
34 CPU A:  writel(newval, ring_ptr);
35 CPU A:  (void)readl(safe_register); /* maybe a config register? */
36 CPU A:  spin_unlock_irqrestore(&dev_lock, flags)