Lines Matching refs:P
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
152 B = 4; Q = P;
153 P = &B D = *Q;
156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
163 Note that CPU 2 will never try and load C into D because the CPU will load P
197 ACCESS_ONCE(Q) = P; smp_read_barrier_depends(); D = ACCESS_ONCE(*Q);
201 Q = LOAD P, D = LOAD *Q
520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
523 ACCESS_ONCE(P) = &B
524 Q = ACCESS_ONCE(P);
533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
550 ACCESS_ONCE(P) = &B
551 Q = ACCESS_ONCE(P);
561 lines. The pointer P might be stored in an odd-numbered cache line, and the
564 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
574 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
577 ACCESS_ONCE(P) = 1
578 Q = ACCESS_ONCE(P);