Lines Matching refs:example
113 For example, consider the following sequence of events:
147 As a further example, consider this sequence of events:
293 using older pre-C11 compilers (for example, gcc 4.6). The portion
559 machines with split caches, so that, for example, one cache bank processes
568 Another example of where data dependency barriers might be required is where a
584 for example. See rcu_assign_pointer() and rcu_dereference() in
589 See also the subsection on "Cache Coherency" for a more thorough example.
618 for load-store control dependencies, as in the following example:
633 to optimize the original example by eliminating the "if" statement
673 Therefore, if you need ordering in this example, you need explicit
674 memory barriers, for example, smp_store_release():
686 ordering is guaranteed only when the stores differ, for example:
702 the needed conditional. For example:
743 evaluation. Consider this example:
750 this example as following, defeating control dependency:
755 This example underscores the need to ensure that the compiler cannot
772 The above two-CPU example will never trigger the assert(). However,
783 assertion can fail after the combined three-CPU example completes. If you
784 need the three-CPU example to provide ordering, you will need smp_mb()
969 In the above example, CPU 2 perceives that B is 7, despite the load of *C
1257 always provided by real computer systems. The following example
1274 This expectation is an example of transitivity: if a load executing on
1280 transitivity. Therefore, in the above example, if CPU 2's load from X
1285 For example, suppose that CPU 2's general barrier in the above example
1295 This substitution destroys transitivity: in this example, it is perfectly
1301 this example runs on a system where CPUs 1 and 2 share a store buffer
1341 One example use for this property is to ease communication between
1388 (*) The compiler is within its rights to reload a variable, for example,
1391 therefore optimize the variable 'tmp' out of our previous example:
1402 For example, the optimized version of this code could result in
1419 what the value will be. For example, if the compiler can prove that
1440 do with the value after the ACCESS_ONCE(). For example, suppose you
1455 wrong thing for shared variables. For example, suppose you have
1475 you tell it not to. For example, consider the following interaction
1518 by something that also accesses 'flag' and 'msg', for example,
1537 as in the following example:
1569 multiple smaller accesses. For example, given an architecture having
1582 use of ACCESS_ONCE() prevents store tearing in the following example:
1587 as in this example:
1606 in this example:
1613 that has been marked volatile. For example, because 'jiffies' is marked
1682 As an example, consider a piece of code that marks an object as being dead
1703 For example, consider a device driver that shares memory with a device
1888 For example, with the following code, the store to *A will always be
1918 As an example, consider the following:
2128 on the separate CPUs. It might, for example, see:
2184 For example:
2205 spinlock, for example:
2272 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2567 i386 architecture machines, for example, this is controlled by way of the
2580 example.
2626 ultimate effect. For example, if two adjacent instructions both load an
2871 operations in exactly the order specified, so that if the CPU is, for example,
2948 in the above example, as there are architectures where a given CPU might
2950 ACCESS_ONCE() does whatever is necessary to prevent this, for example, on