Lines Matching refs:guaranteed
457 pair is -not- guaranteed to act as a full memory barrier. However, after
459 RELEASE on that same variable are guaranteed to be visible. In other
461 previous critical sections for that variable are guaranteed to have
469 between two CPUs or between a CPU and a device. If it can be guaranteed that
686 ordering is guaranteed only when the stores differ, for example:
773 if control dependencies guaranteed transitivity (which they do not),
1284 However, transitivity is -not- guaranteed for read or write barriers.
1668 barrier after it, depending on the function. It isn't guaranteed to
2036 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2171 Without smp_mb__after_unlock_lock(), the accesses are not guaranteed
2557 They are guaranteed to be fully ordered with respect to each other.
2559 They are not guaranteed to be fully ordered with respect to other types of
2564 Whether these are guaranteed to be fully ordered and uncombined with
2570 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2595 the same peripheral are guaranteed to be ordered with respect to each
2921 However, it is guaranteed that a CPU will be self-consistent: it will see its