Lines Matching refs:issued

194  (*) On any given CPU, dependent memory accesses will be issued in order, with
237  (*) It _must_not_ be assumed that independent loads and stores will be issued
375      considered can then perceive.  A data dependency barrier issued by the CPU
379      touched by the load will be perceptible to any loads issued after the data
940 effectively random order, despite the write barrier issued by CPU 1:
1026 some effectively random order, despite the write barrier issued by CPU 1:
1782      Memory operations issued after the ACQUIRE will be completed after the
1785      Memory operations issued before the ACQUIRE may be completed after
1794      Memory operations issued before the RELEASE will be completed before the
1797      Memory operations issued after the RELEASE may be completed before the
1802      All ACQUIRE operations issued before another ACQUIRE operation will be
1807      All ACQUIRE operations issued before a RELEASE operation will be
2220 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2221 before either of the stores issued on CPU 2.
2475      issued prior to unlocking the critical section.
2671 CPU that issued it since it may have been satisfied within the CPU's own cache,