Lines Matching refs:and

6 using the SGDMA and MSGDMA soft DMA IP components. The driver uses the
9 and tested with ARM and NIOS processor hosts seperately. The anticipated use
10 cases are simple communications between an embedded system and an external peer
11 for status and simple configuration of the embedded system.
13 For more information visit www.altera.com and www.rocketboards.org. Support
14 forums for the driver may be found on www.rocketboards.org, and a design used
18 The Triple-Speed Ethernet, SGDMA, and MSGDMA components are all soft IP
19 components that can be assembled and built into an FPGA using the Altera
20 Quartus toolchain. Quartus 13.1 and 14.0 were used to build the design that
22 device tree for the driver, and may be found at rocketboards.org.
24 The driver probe function examines the device tree and determines if the
27 initialize, setup transmits, receives, and interrupt handling primitives for
32 SGDMA support is included for existing designs and reference in case a
33 developer wishes to support their own soft DMA logic and driver support. Any
36 The SGDMA supports only a single transmit or receive operation at a time, and
46 The driver limits PHY operations to 10/100Mbps, and has not yet been fully
63 4) Driver information and notes
68 MSGDMA), and initites a transmit operation. Once the transmit is complete, an
71 resource required to send and track the requested transmit operation.
88 Ethtool is supported. Driver statistics and internal errors can be taken using:
92 The driver is compatible with PAL to work with PHY and GPHY devices.
99  o altera_tse.h: private driver structure and common definitions
104  o altera_sgdmahw.h: SGDMA register and descriptor definitions
105  o altera_msgdmahw.h: MSGDMA register and descriptor definitions
112 debug information, MAC and DMA registers etc.
123 The controller and driver support a mix of IEEE standard defined statistics,
124 RFC defined statistics, and driver or Altera defined statistics. The four
133 The statistics supported by the TSE and the device driver are as follows:
146 an integral number of bytes in length and do not pass the CRC test as the frame
151 integral number of bytes in length and do not pass the CRC test as the frame is
155 Section 5.2.2.1.8. This statistic is the count of data and pad bytes
159 Section 5.2.2.1.14. This statistic is the count of data and pad bytes
212 including error and discarded packets.
216 including error, discarded, unicast, multicast, and broadcast packets.
232 between 65 and 127 octets in length inclusive.
236 between 128 and 255 octets in length inclusive.
240 between 256 and 511 octets in length inclusive.
244 between 512 and 1023 octets in length inclusive.
248 between 1024 and 1518 octets in length inclusive.
251 Altera TSE. This statistics counts the number of received good and errored
252 frames between the length of 1519 and the maximum frame length configured
257 octets, and had either a bad CRC with an integral number of octets (CRC Error)
262 in length and had either a bad CRC with an integral number of octets (CRC