Lines Matching refs:one

21 state bits (one for MMIO and one for DMA, they get set together but can be
54     - For MSIs, we have two windows in the address space (one at the top of
55       the 32-bit space and one much higher) which, via a combination of the
56       address and MSI value, will result in one of the 2048 interrupts per
66     from the CPU address space to the PCI address space.  There is one M32
98     scheme where individual function BARs can be "grouped" to fit in one or
136       than one segment, we end up with more than one PE#.  There is a HW
143       "master PE" which is the one used for DMA, MSIs, etc., and "secondary
172     is a BAR0 for one of the VFs.  Note that even though the VF BAR
178   - M32 window: There's one M32 window, and it is split into 256
189     to a single PE, so it could only isolate one VF.
201     and a 32MB BAR, we could use one M64 window to assign 1MB segments and
213   range to PE#.  Each M64 window defines one MMIO range and this range is
214   divided into 256 segments, with each segment corresponding to one PE.
220   than the number of M64 window segments, so if we map one VF BAR directly
221   to one M64 window, some part of the M64 window will map to another
265   assigned to this one SR-IOV device and none of the space will be