Lines Matching refs:and
9 link used to connect microcontrollers to sensors, memory, and peripherals.
14 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
16 clocking modes through which data is exchanged; mode-0 and mode-3 are most
17 commonly used. Each clock cycle shifts data out and data in; the clock
32 touchscreen sensors and memory chips.
50 SPI is only one of the names used by such four-wire protocols, and
53 Serial Protocol"), PSP ("Programmable Serial Protocol"), and other
56 Some chips eliminate a signal line by combining MOSI and MISO, and
64 Microcontrollers often support both master and slave sides of the SPI
65 protocol. This document (and Linux) currently only supports the master
72 systems boards. SPI is used to control external chips, and it is also a
74 cards, predating MMC cards but using the same connectors and card shape,
78 sensors and codecs, to memory, to peripherals like USB controllers
79 or Ethernet adapters; and more.
85 controller; the reasons to use SPI focus on low cost and simple operation,
86 and if dynamic reconfiguration is important, USB will often be a more
96 It's easy to be confused here, and the vendor documentation you'll
100 clock starts low, so the first (leading) edge is rising, and
112 but their timing diagrams will make the CPOL and CPHA modes clear.
114 In the SPI mode number, CPOL is the high order bit and CPHA is the
116 starting low (CPOL=0) and data stabilized for sampling during the
121 a slave, and the slave can tell the chosen polarity by sampling the
123 support for example both modes 0 and 3: they don't care about polarity,
124 and always clock data in/out on rising clock edges.
130 main source code, and you should certainly read that chapter of the
135 are always executed in FIFO order, and complete asynchronously through
138 a command and then reading its response.
143 processors, and often support both Master and Slave roles.
144 These drivers touch hardware registers and may use DMA.
152 data to filesystems stored on SPI flash like DataFlash; and others might
154 or monitor temperature and voltage levels during industrial processing.
162 using the driver model to connect controller and protocol drivers using
182 physical SPI bus segment, with SCLK, MOSI, and MISO.
200 devices, and the controller may need some platform_data in order to
202 like the physical address of the controller's first register and its IRQ.
208 SPI-capable controllers, and only the ones actually usable on a given
209 board should normally be set up and registered.
312 The widely used "card" style computers bundle memory, cpu, and little else
321 Developer boards often play by different rules than product boards, and one
322 example is the potential need to hotplug SPI devices and/or controllers.
325 up the spi bus master, and will likely need spi_new_device() to provide the
385 + when bidirectional reads and writes start ... by how its
390 (two pointers, maybe the same one in both cases) and half
397 + whether the chipselect becomes inactive after a transfer and
402 transfer in that atomic group, and potentially saving costs
403 for chip deselect and select operations.
405 - Follow standard kernel rules, and provide DMA-safe buffers in
415 issued in any context (irq handler, task, etc) and completion
417 After any detected error, the chip is deselected and processing
420 - There are also synchronous wrappers like spi_sync(), and wrappers
421 like spi_read(), spi_write(), and spi_write_then_read(). These
422 may be issued only in contexts that may sleep, and they're all
423 clean (and small, and "optional") layers over spi_async().
425 - The spi_write_then_read() call, and convenience wrappers around
429 and reading a sixteen bit response -- spi_w8r16() being one its
446 - I/O buffers use the usual Linux rules, and must be DMA-safe.
450 - The spi_message and spi_transfer metadata used to glue those
455 If you like, spi_message_alloc() and spi_message_free() convenience
456 routines are available to allocate and zero-initialize an spi_message
466 Use spi_alloc_master() to allocate the master, and spi_master_get_devdata()
479 bus number (maybe the same as the platform device ID) and three methods
480 used to interact with the SPI core and SPI protocol drivers. It will
482 and those methods.)
486 controller and any predeclared spi devices will be made available, and
499 and spi_board_info for devices connected to it would use that number.
501 If you don't have such hardware-assigned bus number, and for some reason
510 This sets up the device clock rate, SPI mode, and word sizes.
511 Drivers may change the defaults provided by board_info, and then
536 that there are no more messages pending in the queue and it may
553 transfer. This may sleep. Note: transfer_one and transfer_one_message
566 transfer happens and its complete() callback is issued. The two
567 will normally happen later, after other transfers complete, and
569 method is not used on queued controllers and must be NULL if
570 transfer_one_message() and (un)prepare_transfer_hardware() are
578 the message queue has the upside of centralizing a lot of code and
590 often DMA (especially if the root filesystem is in SPI flash), and
594 queue, and then start some asynchronous transfer engine (unless it's