Lines Matching refs:DMA
8 This is due to DMA constraints, which transfers only planes of 8 byte
20 capture. The new buffers are "appended" at the tail of the DMA chain, and
38 | | DMA: stop | | DMA: stop | |
45 | | DMA hotlink missed | | Capture running | |
48 | | DMA: stop | / | DMA: run | | |
50 | ^ /DMA still | | channels |
51 | | capture list / running | DMA Irq End | not |
58 | DMA: run | | DMA: run | |
67 | DMA: run | | DMA: stop |
76 - "DMA: stop" means all 3 DMA channels are stopped
77 - "DMA: run" means at least 1 DMA channel is still running
79 DMA usage
81 a) DMA flow
85 starts the DMA chain.
87 The DMA chain starts transferring data into videobuffer RAM pages.
88 When all pages are transferred, the DMA irq is raised on "ENDINTR" status
90 The DMA irq handler marks the videobuffer as "done", and removes it from
92 Meanwhile, the next videobuffer (if there is one), is transferred by DMA
94 On the DMA irq of the last videobuffer, the QCI is stopped.
96 b) DMA prepared buffer will have this structure
130 c) DMA hot chaining timeslice issue
132 As DMA chaining is done while DMA _is_ running, the linking may be done
133 while the DMA jumps from one Videobuffer to another. On the schema, that
136 - DMA chain is Videobuffer1 + Videobuffer2
138 - DMA controller finishes Videobuffer2, and DMA stops
145 +----+ +-- DMA DDADR loads DDADR_STOP
150 - the DMA irq handler is called, which terminates Videobuffer2
151 - Videobuffer3 capture is not scheduled on DMA chain (as it stopped !!!)
160 DMA DDADR still is DDADR_STOP
163 This checks if the DMA is finished and a buffer is still on the
165 and Videobuffer3 is scheduled on DMA chain.
166 - the DMA irq handler finishes
168 Note: if DMA stops just after pxa_camera_check_link_miss() reads DDADR()
169 value, we have the guarantee that the DMA irq handler will be called back
170 when the DMA will finish the buffer, and pxa_camera_check_link_miss() will