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16 One of the most complicated parts of the X86 platform, and specifically,
18 and the complexity of emulating those devices. In addition, virtualization of
23 present some of the problems which arise and solutions available, giving
26 The purpose of this document is to collect data and information relevant to
28 information relevant to KVM and hardware-based virtualization.
34 First we discuss the basic hardware devices available. TSC and the related
35 KVM clock are special enough to warrant a full exposition and are described in
41 or PIT. The PIT has a fixed frequency 1.193182 MHz base clock and three
43 These three channels can be configured in different modes and have individual
44 counters. Channel 1 and 2 were not available for general use in the original
45 IBM PC, and historically were connected to control RAM refresh and the PC
47 and a separate physical PIT is not used.
52 has a connected gate input, required for modes 1 and 5. The gate line is
81 when the gate is high (always true for timers 0 and 1). When the count
90 reaches 1, the output goes low for one count and then returns high. The value
91 is reloaded and the countdown automatically resumes. If the gate line goes
96 determines the length of the pulse, which alternates between high and low
97 when zero is reached. The count only proceeds when gate is high and is
100 If the count is even, the clock remains high for N/2 counts and low for N/2
101 counts; if the clock is odd, the clock is high for (N+1)/2 counts and low
106 Mode 4: Software Strobe. After programming this mode and loading the counter,
108 goes low for 1 clock cycle and returns high. The counter is not reloaded.
111 Mode 5: Hardware Strobe. After programming and loading the counter, the
114 the output goes low for 1 clock cycle and then returns high. The counter is
118 command port, 0x43 is used to set the counter and mode for each of the three
130 sample and hold the count to be read in port 0x40;
135 set timer to read LSB only and force MSB to zero;
139 set timer to read MSB only and force LSB to zero;
183 time clock. The original device is now obsolete, and usually emulated by the
184 system chipset, sometimes by an HPET and some frankenstein IRQ routing.
188 of the CMOS and read of the RTC require lock protection (in addition, it is
190 access, as they could corrupt kernel reads and writes of CMOS memory).
193 can function as a periodic timer, an additional once a day alarm, and can issue
256 (*) location vendor specific and now determined from ACPI global tables
260 On Pentium and later processors, an on-board timer is available to each CPU
262 accessed through memory-mapped registers and provides interrupt service to each
263 CPU, used for IPIs and local timer interrupts.
265 Although in theory the APIC is a safe and stable source for local interrupts,
266 in practice, many bugs and glitches have occurred due to the special nature of
268 the use of the APIC and that workarounds may be required. In addition, some of
273 Since the APIC is documented quite well in the Intel and AMD manuals, we will
276 of one-shot or periodic operation, and is based on the bus clock divided down
281 HPET is quite complex, and was originally intended to replace the PIT / RTC
287 The HPET spec is rather loose and vague, requiring at least 3 hardware timers,
290 frequency, error and slew.
294 in any given system). The HPET is also memory-mapped, and its presence is
302 Several cards, both proprietary (watchdog boards) and commonplace (e1000) have
305 a clocksource for a Linux or other kernel has not yet been attempted and is in
307 timer device would require additional support to be virtualized properly and is
322 was only possible to write the low 32-bits of the 64-bit counter, and the upper
324 0Fh, for models 3, 4 and 6, and family 06h, models e and f, this restriction
325 has been lifted and all 64-bits are writable. On AMD systems, the ability to
328 The TSC is accessible from CPL-0 and conditionally, for CPL > 0 software by
338 Both VMX and SVM provide extension fields in the virtualization hardware which
350 The BIOS may attempt to resynchronize the TSCs during the poweron process and
360 3.2) TSC and CPU hotplug
368 small, may be exposed to the OS and any virtualization environment.
370 3.3) TSC and multi-socket / NUMA
375 perfectly matched frequency, and temperature and electrical variations will
376 cause the CPU clocks, and thus the TSCs to drift over time. Depending on the
377 exact clock and bus design, the drift may or may not be fixed in absolute
378 error, and may accumulate over time.
382 clock frequency and harmonics of it, which may be required to pass FCC
383 standards for telecommunications and computer equipment.
388 3.4) TSC and C-states
390 C-states, or idling states of the processor, especially C1E and deeper sleep
393 is resumed. Such CPUs must be detected and flagged by the operating system
394 based on CPU and chipset identifications.
402 may or may not run the TSC at the same rate, and because the frequency change
405 not be a stable time source, and must be calibrated against a known, stable,
409 dependent and must be determined by inspecting CPUID, chipset or vendor
419 3.6) TSC and STPCLK / T-states
423 an overheating condition, and typically, there is no way to detect that this
428 VMX provides conditional trapping of RDTSC, RDMSR, WRMSR and RDTSCP
431 field specified in the VMCS. Special instructions must be used to read and
436 SVM provides conditional trapping of RDTSC, RDMSR, WRMSR and RDTSCP
461 the host and, potentially, a number of virtual machines. Thus the virtual
465 virtual interrupt sources are disabled, and the machine may still be preempted
467 of machine interrupts and the associated clock sources are no longer completely
482 be able to deliver the proper number of interrupts per second, and so guest
493 where host load or guest lag is too much to compensate for, and thus another
495 ticks and compensate for them internally. Although promising in theory, the
496 implementation of this policy in Linux has been extremely error prone, and a
500 Windows uses periodic RTC clocking as a means of keeping time internally, and
505 4.2) TSC sampling and serialization
509 many problems unique to its nature as a local, potentially unstable and
517 measurement with the TSC, and requires a serializing instruction, such as CPUID
520 Since CPUID may actually be virtualized by a trap and emulate mechanism, this
522 accurate time stamp counter reading may therefore not always be available, and
545 at the rate of jiffies, and possibly in catchup modes, at a much larger step.
547 This aliasing requires care in the computation and recalibration of kvmclock
548 and any other values derived from TSC computation (such as TSC virtualization
555 delivered, and after which, the guest time may need to be caught up. NTP may
566 simply storing multipliers and offsets against the TSC for the guest to convert
571 Since scheduling may be based on precise timing and firing of interrupts, the
573 virtualization. In theory, the effect is random and should be universally
587 spurious and can be ignored, but in some circumstances it may be necessary to
590 4.7) Delays and precision timing
592 Precise timing and delays may not be possible in a virtualized system. This
594 compensate for slower I/O to and from devices. The first issue is not solvable
603 4.8) Covert channels and leaks
608 red-pill type detection), and it may allow information to leak between guests