Lines Matching refs:as

46 speaker.  Now the PIT is typically integrated as part of an emulated chipset
51 available, but not all modes are available to all timers, as only timer 2
53 controlled by port 61h, bit 0, as illustrated in the following diagram.
146 0100 - Latch Timer 1 count for port 0x41 - as described above
147 0101 - Set Timer 1 LSB mode for port 0x41 - as described above
148 0110 - Set Timer 1 MSB mode for port 0x41 - as described above
149 0111 - Set Timer 1 16-bit mode for port 0x41 - as described above
151 1000 - Latch Timer 2 count for port 0x42 - as described above
152 1001 - Set Timer 2 LSB mode for port 0x42 - as described above
153 1010 - Set Timer 2 MSB mode for port 0x42 - as described above
154 1011 - Set Timer 2 16-bit mode for port 0x42 as described above
189 dangerous to allow userspace utilities such as hwclock to have direct RTC
190 access, as they could corrupt kernel reads and writes of CMOS memory).
193 can function as a periodic timer, an additional once a day alarm, and can issue
199 in progress, as indicated in the status register.
261 as part of the Advanced Programmable Interrupt Controller.  The APIC is
282 support of the X86 PC.  It remains to be seen whether that will be the case, as
284 systems designated as legacy free may support only the HPET as a hardware timer
292 In general, the HPET is recommended as a high precision (compared to PIT /RTC)
293 time source which is independent of local variation (as there is only one HPET
298 document, as it is also very well documented elsewhere.
306 general frowned upon as not playing by the agreed rules of the game.  Such a
308 not considered important at this time as no known operating system does this.
315 instruction cycles issued by the processor, which can be used as a measure of
319 The TSC is represented internally as a 64-bit MSR which can be read with the
351 the operating system or other system software may attempt to do this as well.
381 cores.  This technique, known as spread-spectrum clocking, reduces EMI at the
391 states may be problematic for TSC as well.  The TSC may stop advancing in such
466 at any time.  This causes problems as the passage of real time, the injection
470 This same problem can occur on native hardware to a degree, as SMM mode may
484 is selected, such as 1000 HZ, which is unfortunately the default for many Linux
500 Windows uses periodic RTC clocking as a means of keeping time internally, and
509 many problems unique to its nature as a local, potentially unstable and
517 measurement with the TSC, and requires a serializing instruction, such as CPUID
524 the TSC as seen from other CPUs, even in an otherwise perfectly synchronized
538 Re-calibrating this computation may actually cause time, as computed after the
548 and any other values derived from TSC computation (such as TSC virtualization
556 be able to help to some degree here, as the clock correction required is
562 migrating to a faster machine may preclude the use of a passthrough TSC, as a
564 advancing faster than usual.  A slower clock is less of a problem, as it can
574 distributed, but in contrived as well as real scenarios (guest device access,
584 Watchdog timers, such as the lock detector in Linux may fire accidentally when
607 time.  This may allow the guest to infer the presence of a hypervisor (as in a
609 by using CPU utilization itself as a signalling channel.  Preventing such