Lines Matching refs:buffers

95 sized buffers (even though such buffers are used by Xillybus under the hood).
102 up the DMA buffers and character devices accordingly. As a result, a single
153 room in the buffers to store any of the data in the buffers.
222 * bufnum: The number of buffers allocated for this pipe. Always a power of two.
269 sides, the implementation relies on a set of DMA buffers which is allocated
272 FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the
292 filled buffers being sent) and a latency held fairly low for tails of data.
295 partial DMA buffers is somewhat different, though. The user can tell the
296 driver to submit all data it has in the buffers to the FPGA, by issuing a
305 to lay around in the DMA buffers between read() and write() anyhow.
348 xilly_setupchannels() functions allocates these buffers by requesting whole
349 pages from the kernel, and diving them into DMA buffers as necessary. Since
350 all buffers' sizes are powers of two, it's possible to pack any set of such
351 buffers, with a maximal waste of one page of memory.
353 All buffers are allocated when the driver is loaded. This is necessary,