132 	int idx;  member
157 	idx0 = ev67_mapping[evtype[0]-1].idx;  in ev67_check_constraints()
198 	event[0]->hw.idx = idx0;  in ev67_check_constraints()
201 		event[1]->hw.idx = idx0 ^ 1;  in ev67_check_constraints()
232 static inline void alpha_write_pmc(int idx, unsigned long val)  in alpha_write_pmc()  argument
234 	val &= alpha_pmu->pmc_count_mask[idx];  in alpha_write_pmc()
235 	val <<= alpha_pmu->pmc_count_shift[idx];  in alpha_write_pmc()
236 	val |= (1<<idx);  in alpha_write_pmc()
240 static inline unsigned long alpha_read_pmc(int idx)  in alpha_read_pmc()  argument
245 	val >>= alpha_pmu->pmc_count_shift[idx];  in alpha_read_pmc()
246 	val &= alpha_pmu->pmc_count_mask[idx];  in alpha_read_pmc()
252 				struct hw_perf_event *hwc, int idx)  in alpha_perf_event_set_period()  argument
276 	if (unlikely(left < alpha_pmu->pmc_left[idx]))  in alpha_perf_event_set_period()
277 		left = alpha_pmu->pmc_left[idx];  in alpha_perf_event_set_period()
279 	if (left > (long)alpha_pmu->pmc_max_period[idx])  in alpha_perf_event_set_period()
280 		left = alpha_pmu->pmc_max_period[idx];  in alpha_perf_event_set_period()
284 	alpha_write_pmc(idx, (unsigned long)(-left));  in alpha_perf_event_set_period()
307 					struct hw_perf_event *hwc, int idx, long ovf)  in alpha_perf_event_update()  argument
314 	new_raw_count = alpha_read_pmc(idx);  in alpha_perf_event_update()
320 	delta = (new_raw_count - (prev_raw_count & alpha_pmu->pmc_count_mask[idx])) + ovf;  in alpha_perf_event_update()
326 		delta += alpha_pmu->pmc_max_period[idx] + 1;  in alpha_perf_event_update()
402 			cpuc->current_idx[j] != pe->hw.idx) {  in maybe_change_configuration()
413 		int idx = hwc->idx;  in maybe_change_configuration()  local
416 			alpha_perf_event_set_period(pe, hwc, idx);  in maybe_change_configuration()
417 			cpuc->current_idx[j] = idx;  in maybe_change_configuration()
496 			int idx = cpuc->current_idx[j];  in alpha_pmu_del()  local
509 			alpha_perf_event_update(event, hwc, idx, 0);  in alpha_pmu_del()
512 			cpuc->idx_mask &= ~(1UL<<idx);  in alpha_pmu_del()
527 	alpha_perf_event_update(event, hwc, hwc->idx, 0);  in alpha_pmu_read()
537 		cpuc->idx_mask &= ~(1UL<<hwc->idx);  in alpha_pmu_stop()
542 		alpha_perf_event_update(event, hwc, hwc->idx, 0);  in alpha_pmu_stop()
547 		wrperfmon(PERFMON_CMD_DISABLE, (1UL<<hwc->idx));  in alpha_pmu_stop()
561 		alpha_perf_event_set_period(event, hwc, hwc->idx);  in alpha_pmu_start()
566 	cpuc->idx_mask |= 1UL<<hwc->idx;  in alpha_pmu_start()
568 		wrperfmon(PERFMON_CMD_ENABLE, (1UL<<hwc->idx));  in alpha_pmu_start()
669 	hwc->idx = PMC_NO_INDEX;  in __hw_perf_event_init()
815 	int idx, j;  in alpha_perf_event_irq_handler()  local
836 	idx = la_ptr;  in alpha_perf_event_irq_handler()
839 		if (cpuc->current_idx[j] == idx)  in alpha_perf_event_irq_handler()
854 		pr_warning("PMI: No event at index %d!\n", idx);  in alpha_perf_event_irq_handler()
860 	alpha_perf_event_update(event, hwc, idx, alpha_pmu->pmc_max_period[idx]+1);  in alpha_perf_event_irq_handler()
863 	if (alpha_perf_event_set_period(event, hwc, idx)) {  in alpha_perf_event_irq_handler()